rtldesign
There are 6 repositories under rtldesign topic.
avashist003/SystemVerilog_Design_Verification
Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
164adityakumar/Image_Encryption_I-CHIP
This project aims to design a hardware encryption and decryption scheme for the Data Encryption Standard (DES) algorithm
iammituraj/reset_and_cdc_synchronizers
Reset and CDC synchronizers developed in Verilog/System Verilog.
iammituraj/tweak_circuits
Tweak circuits designed in VHDL/Verilog like CDC synchronizers: Pulse synchronizer, Reset synchronizer, Two-flop synchronizer, Edge detectors, Pulse generators, Clock gating etc.
princeranjan03/ImageEncryption_I-CHIP
This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.
sidhantp1906/4-bit-first-divider
4 bit divider design using first divider algorithm