This repository consists of collaterals needed for "System Design and Modelling using Verilog" workshop. All verilog files and testbench uploaded here are used in conjunction with Lecture videos shown in workshop. If you wish to use them, please feel free to contact kunalpghosh@gmail.com in case you find issues
This repo needs iverilog and gtkwave open-source EDA tools. With that said, it can also be run using commercial EDA tools There is verilog file and an associated testbench tb_(verilog) file. The way to run the files are
iverilog <verilog>.v tb_<verilog>.v // This will generate VCD file
gtkwave <verilog>.vcd // This command is used to view the waveforms
Detailed descriptions are provided in workshop. Universities and Corporates can contact kunalpghosh@gmail.com for workshop content details and timings