kunalg123

device_modelling

Scripts for 1D- and 2D- NMOS device modelling and simulation

flipflop_design

This project has files needed to design and characterise flipflop

icc2_workshop_collaterals

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainings

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

raven_spi_hierarchical_physical_design

Commit files needed for SPI hierarchical implementation

riscv_workshop_collaterals

This repository is created for conducting RISC-V 5-day workshops

sky130CircuitDesignWorkshop

sky130RTLDesignAndSynthesisWorkshop

sta_workshop

This repository has all collateral for STA workshop

vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

kunalg123/vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

kunalg123/icc2_workshop_collaterals

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainings

kunalg123/riscv_workshop_collaterals

This repository is created for conducting RISC-V 5-day workshops

kunalg123/flipflop_design

This project has files needed to design and characterise flipflop

kunalg123/sky130RTLDesignAndSynthesisWorkshop

kunalg123/picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

kunalg123/device_modelling

Scripts for 1D- and 2D- NMOS device modelling and simulation

kunalg123/raven_spi_hierarchical_physical_design

Commit files needed for SPI hierarchical implementation

kunalg123/sky130CircuitDesignWorkshop

kunalg123/sta_workshop

This repository has all collateral for STA workshop

kunalg123/rvmyth

kunalg123/SystemDesignWorkshopCollaterals

kunalg123/avsddac_3v3

kunalg123/ngspice_labs

SPICE simulation labs for workshop

kunalg123/VSD-HDP

all material for the VSD-HDP program

kunalg123/manhattan-project_HDP