kunalg123/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
VerilogApache-2.0
Issues
- 0
helpppppp meeeeeee !!!
#10 opened by Vikraman46 - 2
opensource_eda_tool_install.sh installs cmake at /usr/local without any alternative
#8 opened by ssmolov - 1
- 2
STA failing
#3 opened by dsnaveen1 - 0
unable to fix error in lvs
#6 opened by dsnaveen1 - 1
The vsdflow in the example stuck at last line "Info: Initializing number of threads, libraries, sdc, verilog netlist path... " Directory not getting created
#4 opened by rakeshpatil1983 - 3
- 0
Issue when installing vsdflow
#1 opened