This project contains a pipelined CPU for LC3 instruction written in Verilog HDL. This project was finished in Quartus 9.0 and verified in FPGA board. The pipelined CPU contains classical five stages: fetch, decode, execute, access memory and write back.
lanwuwei/LC3-pipeline
This project contains a pipelined CPU for LC3 instruction written in Verilog HDL.
Verilog