lanxingyuehai's Stars
pConst/basic_verilog
Must-have verilog systemverilog modules
adki/gen_amba_2021
AMBA bus generator including AXI4, AXI3, AHB, and APB
openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
hellovimo/uvm_testbench_gen
Novel GUI Based UVM Testbench Template Builder
lowRISC/opentitan
OpenTitan: Open source silicon root of trust
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
massgravel/Microsoft-Activation-Scripts
Open-source Windows and Office activator featuring HWID, Ohook, KMS38, and Online KMS activation methods, along with advanced troubleshooting.
iptv-org/iptv
Collection of publicly available IPTV channels from all over the world
aliyun/plugsched
Live upgrade Linux kernel scheduler subsystem
getlantern/download
Lantern官方版本下载 蓝灯 翻墙 代理 科学上网 外网 加速器 梯子 路由 proxy vpn circumvention gfw
taichi-ishitani/tvip-axi
AMBA AXI VIP
rggen/rggen
Code generation tool for control and status registers
Juniper/simple_reg_model
System verilog register model for uvm testbenches.
avashist003/UVM_Verification
Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
olofk/edalize
An abstraction library for interfacing EDA tools
cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
QSCTech/zju-icicles
浙江大学课程攻略共享计划
pjialin/py12306
🚂 12306 购票助手,支持集群,多账号,多任务购票以及 Web 页面管理
apache/tvm
Open deep learning compiler stack for cpu, gpu and specialized accelerators
doctest/doctest
The fastest feature-rich C++11/14/17/20/23 single-header testing framework
facert/awesome-spider
爬虫集合
nelsoncsc/ISP_UVM
A Framework for Design and Verification of Image Processing Applications using UVM
nvdla/hw
RTL, Cmodel, and testbench for NVDLA
datawhalechina/pumpkin-book
《机器学习》(西瓜书)公式详解