lazarvulic99
BSc in Computer Engineering and Information Theory. MSc student, Software Engineering, at School of Electrical Engineering, University of Belgrade.
Faculty of Electrical EngineeringBelgrade, Serbia
Pinned Repositories
Assembler-Project---AR-19-20
Simple assembler functionalities
Computer-Networks-Project
Some network monitoring concepts
Java-SQL-Queries
SQL Queries implemented using Java
Kernel---Operating-System
Preemptive, multithread operational system. System that supports Thread, Semaphore and Event concept. Eclipse IDE and Borland C++ 3.1 compiler for 8086 were used.
lazarvulic99
Config files for my GitHub profile.
MJCompiler
A compiler for MicroJava. Lexical analysis with syntax and semantical error catching. Bytecode generating for MJ virtual machine.
Object-oriented-programming-in-Cpp-
Object-oriented-programming-in-Java
JAVA games with GUI and Threads Concept
Rolling-the-Dice
Rolling the Dice console game
Secure-Software-Development-Application
Application written in Java using Sping, Thymeleaf and H2 database in collaboration with ETF and Zühlke Serbia. SQL Injection, XSS, CSRF attacks and prevention. Static analysis using SonarQube, dynamic analysis using OWASP ZAP. Implemented authorization and authentication using TOTP authenticator. DevOps - concepts of logging and auditing.
lazarvulic99's Repositories
lazarvulic99/Assembler-Project---AR-19-20
Simple assembler functionalities
lazarvulic99/Computer-Networks-Project
Some network monitoring concepts
lazarvulic99/Java-SQL-Queries
SQL Queries implemented using Java
lazarvulic99/Kernel---Operating-System
Preemptive, multithread operational system. System that supports Thread, Semaphore and Event concept. Eclipse IDE and Borland C++ 3.1 compiler for 8086 were used.
lazarvulic99/lazarvulic99
Config files for my GitHub profile.
lazarvulic99/MJCompiler
A compiler for MicroJava. Lexical analysis with syntax and semantical error catching. Bytecode generating for MJ virtual machine.
lazarvulic99/Object-oriented-programming-in-Cpp-
lazarvulic99/Object-oriented-programming-in-Java
JAVA games with GUI and Threads Concept
lazarvulic99/Rolling-the-Dice
Rolling the Dice console game
lazarvulic99/Secure-Software-Development-Application
Application written in Java using Sping, Thymeleaf and H2 database in collaboration with ETF and Zühlke Serbia. SQL Injection, XSS, CSRF attacks and prevention. Static analysis using SonarQube, dynamic analysis using OWASP ZAP. Implemented authorization and authentication using TOTP authenticator. DevOps - concepts of logging and auditing.
lazarvulic99/Some-MATLAB-GNU-Octave-examples-from-Digital-signal-processing
Some simple filters implementation for data signal proccessing and others
lazarvulic99/STM32F103x6-Modified-Homework-Project
Implementation of simple STM32F103x6 microcontroller using multiple environments
lazarvulic99/SystemVerilog-Verification---Register-functionalities
Simple register realisation for SystemVerilog Verification
lazarvulic99/Tara---National-Park-Reservation-Web-Application---Front
Simple Web application for creating hotel reservations, only fronted implemented
lazarvulic99/Tic-Tac-Toe
Simple Tic-Tac-Toe game written in Java using Java AWT Events, Java Util and Java Swing
lazarvulic99/Tokyo-2021---Web-Application
Web app for Tokyo 2021 Olympics Games (complete players medal statistics, players from all countries, all sports and disciplines, tournaments making...) Implemented using multiple programming techniques.
lazarvulic99/Translation-toolchain-and-emulator-for-abstract-computer-system
Output .o file in structure similar to one in ELF is made from one input .s file in assembly language similar to x86. Two or more .o files will be merged in one .hex file, that will be the input file for our emulator. Emulator will execute .hex file and the output will be shown in console.
lazarvulic99/UI-UX-Zoo-Park
UI/UX for Zoo Park in Belgrade, made with Figma. Documentation provided.
lazarvulic99/Verilog---Module-synthesis
Simple module realisation for Verilog Synthesis
lazarvulic99/Verilog-Module-Simulation
Simple module realisation for Verilog Simulation