leochand101
Senior Scientist with Alphacore, Circuits, EDA, auto-place and route, CAD, Testing, modelling are some of my interests. PhD in EE with ASU
Pinned Repositories
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
doc_history
History of random searches and examples
FreeRouting
Printed Circuit Board Routing Software from FreeRouting.net
gdsfactory
Python package to generate GDS layouts.
handson-ml2
A series of Jupyter notebooks that walk you through the fundamentals of Machine Learning and Deep Learning in Python using Scikit-Learn, Keras and TensorFlow 2.
kicad_freerouting-plugin
KiCad FreeRouting.jar round trip invoker
Open-GPGPU-FlexGrip-
FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
OpenFASOC
Fully Open Source FASOC generators built on top of OpenROAD
OpenFPGA
An Open-source FPGA IP Generator
OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
leochand101's Repositories
leochand101/cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
leochand101/doc_history
History of random searches and examples
leochand101/FreeRouting
Printed Circuit Board Routing Software from FreeRouting.net
leochand101/gdsfactory
Python package to generate GDS layouts.
leochand101/handson-ml2
A series of Jupyter notebooks that walk you through the fundamentals of Machine Learning and Deep Learning in Python using Scikit-Learn, Keras and TensorFlow 2.
leochand101/kicad_freerouting-plugin
KiCad FreeRouting.jar round trip invoker
leochand101/Open-GPGPU-FlexGrip-
FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
leochand101/OpenFASOC
Fully Open Source FASOC generators built on top of OpenROAD
leochand101/OpenFPGA
An Open-source FPGA IP Generator
leochand101/OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
leochand101/PyBERT
Serial communication link bit error rate tester simulator, written in Python.
leochand101/pyoa
Donald Amundson's Python interface to OpenAccess IC design data API
leochand101/pyspectre
Python interface for Cadence Spectre
leochand101/PySpice
Simulate electronic circuit using Python and the Ngspice / Xyce simulators
leochand101/skidl
SKiDL is a module that extends Python with the ability to design electronic circuits.
leochand101/sky130_klayout_pdk
Skywater 130nm Klayout Device Generators PDK
leochand101/SOFA
SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
leochand101/tf_import
Reads a Cadence techfile into KLayout and produces layer properties from it
leochand101/VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA