leochand101
Senior Scientist with Alphacore, Circuits, EDA, auto-place and route, CAD, Testing, modelling are some of my interests. PhD in EE with ASU
leochand101's Stars
mathworks/MATLAB-Simulink-Challenge-Project-Hub
This MATLAB and Simulink Challenge Project Hub contains a list of research and design project ideas. These projects will help you gain practical experience and insight into technology trends and industry directions.
sharkdp/binocle
a graphical tool to visualize binary data
hughperkins/VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
IHP-GmbH/IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
joamatab/awesome_photonics
😎 curated list of open source photonics projects
trilomix/GDS3D
GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://github.com/skuep/GDS3D) as the same source and add few improvement like compression with server/client process. This release add two major feature with are assembly and export 3D model for GMSH. Assembly: this mean it’s possible to merge multi GDS (with different technologies) I also try to improve net highlight.
NVlabs/verilog-eval
Verilog evaluation benchmark for large language model
SparcLab/OpenSERDES
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
cuhk-eda/cu-gr
CUGR, VLSI Global Routing Tool Developed by CUHK
sandialabs/cross-sim
CrossSim: accuracy simulation of analog in-memory computing
Accelergy-Project/timeloop-accelergy-exercises
Exercises for exploring the Fibertree, Timeloop and Accelergy tools
Jerc007/Open-GPGPU-FlexGrip-
FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
Kuree/pysv
Running Python code in SystemVerilog
patrickschulz/openPCells
Parametric layout generator for digital, analog and mixed-signal integrated circuits
asicsforthemasses/LunaPnR
LunaPnR is a place and router for integrated circuits
mit-emze/cimloop
dan-fritchman/Netlist
Parsing and generating popular formats of circuit netlist
klayoutmatthias/tf_import
Reads a Cadence techfile into KLayout and produces layer properties from it
muhammadaldacher/Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
arutema47/sar-adc
Model SAR ADC with python!
rmanohar/actsim
Simulator for ACT hardware description language
asyncvlsi/interact
Command-line design environment for asynchronous logic
wrcad/MRouter
A maze router
basemhesham/Digital-Design-of-FIR-Filter-Transposed-Structure
Design and Validation of a Customizable 50th-Order Low-Pass FIR Filter. Transitioning from MATLAB Modeling to Verilog RTL Design and simulation Testing.
harwHarw03/adaptive-filter-verilog
LMS Adaptive Filter implementation using Vedic Multiplication and Manchester Carry Chain ADder
iammituraj/reset_and_cdc_synchronizers
Reset and CDC synchronizers developed in Verilog/System Verilog.
k-nasim/synchronizers-CDC
basic synchronizers used in CDC paths ( Verilog)
Francis3436/Verilog-Quadcopter-Project-ECE-551
Verilog Codes for Quadcopter Project
jshaker000/pam-cdr
ThomasPluck/Hdl21Schematics
Hdl21 Schematics