Pinned Repositories
altera-makefiles
Makefiles & scripts for Altera FPGA projects
avalon-1wire-master
1-wire bus master core with Altera Avalon-MM slave interface
avalon-1wire-master-example
Example of using Avalon 1-wire master core with DS18B20 sensors
avmm-lvds-bridge
Cores for transfer Avalon-MM transaction through LVDS SERDES interface
emif16-avmm-bridge
Module for connect TI DSP to Altera Qsys Interconnect through EMIF16 interface
jtag_dpi
JTAG DPI module for SystemVerilog RTL simulations
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
SD-card-controller
WISHBONE SD Card Controller IP Core
lexgolovchenko's Repositories
lexgolovchenko/avmm-lvds-bridge
Cores for transfer Avalon-MM transaction through LVDS SERDES interface
lexgolovchenko/avalon-1wire-master
1-wire bus master core with Altera Avalon-MM slave interface
lexgolovchenko/emif16-avmm-bridge
Module for connect TI DSP to Altera Qsys Interconnect through EMIF16 interface
lexgolovchenko/altera-makefiles
Makefiles & scripts for Altera FPGA projects
lexgolovchenko/avalon-1wire-master-example
Example of using Avalon 1-wire master core with DS18B20 sensors
lexgolovchenko/jtag_dpi
JTAG DPI module for SystemVerilog RTL simulations
lexgolovchenko/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
lexgolovchenko/SD-card-controller
WISHBONE SD Card Controller IP Core