lexgolovchenko

lexgolovchenko's Stars

• esynr3z/svjson

  🇯 JSON encoder and decoder in pure SystemVerilog

  Language:SystemVerilog6

• alexforencich/verilog-axis

  Verilog AXI stream components for FPGA implementation

  Language:Python684215

• ghdl/ghdl

  VHDL 2008/93/87 simulator

  Language:VHDL2.3k353

• ThalesGroup/udp-offload-engine

  UDP-IP stack accelerator and is able to send and receive data through Ethernet link

  Language:VHDL102

• Geontech/vrtgen

  Language:C++82

• RedhawkSDR/VITA49

  rh.VITA49 shared library

  Language:C++1917

• tmeissner/psl_with_ghdl

  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

  Language:VHDL623

• rafamadriz/friendly-snippets

  Set of preconfigured snippets for different languages.

  Language:Lua1.8k411

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2k626

• hdl-registers/hdl-registers

  An open-source HDL register code generator fast enough to run in real time.

  Language:Python252

• Juniper/open-register-design-tool

  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  Language:Verilog18467

• ttroy50/cmake-examples

  Useful CMake Examples

  Language:CMake12.1k2.5k

• cphurley82/tlm2-gtestbench

  SystemC TLM2 testbench using gtest framework.

  Language:C++71

• anikau31/systemc-clang

  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.

  Language:C++7019

• salmer/CppDeveloperRoadmap

  The roadmap for learning the C++ programming language for beginners and experienced devs.

  2.7k281

• intel/systemc-compiler

  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

  Language:C++23236

• windwp/nvim-autopairs

  autopairs for neovim written in lua

  Language:Lua3k111

• maxnilz/compiledb-plus

  Tool for generating Clang's JSON Compilation Database files for make-based build systems.

  Language:Python2

• JulianKemmerer/PipelineC

  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

  Language:Python56646

• cruxopen/openISP

  Image Signal Processor

  Language:Python1k374

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C2.8k538

• Xilinx/HLS

  Vitis HLS LLVM source code and examples

  37555

• google/xls

  XLS: Accelerated HW Synthesis

  Language:C++1.2k166

• ossu/computer-science

  :mortar_board: Path to a free self-taught education in Computer Science!

  166k20.9k

• tavigul/teachyourselfCS-KG

  Kyrgyz translation of https://teachyourselfcs.com

  5

• akiyosi/goneovim

  A GUI frontend for neovim.

  Language:Go2.3k60

• ranger/ranger

  A VIM-inspired filemanager for the console

  Language:Python15.2k892

• hlslibs/ac_types

  Algorithmic C Datatypes

  Language:C++10934

• suoto/hdl_checker

  Repurposing existing HDL tools to help writing better code

  Language:Python18722

• folke/lazy.nvim

  💤 A modern plugin manager for Neovim

  Language:Lua13k310