lexgolovchenko's Stars
wallento/cocotbext-wishbone
themperek/cocotb-test
Unit testing for cocotb
Madhumitha2001/MPPT
A solar charge controller with MPPT extract maximum power from a photovoltaic panel to charge the battery
esynr3z/corsair
Control and Status Register map generator for HDL projects
hundredrabbits/awesome-uxn
Awesome things from the community
zhelnio/schoolRISCV
CPU microarchitecture, step by step
enjoy-digital/litesdcard
Small footprint and configurable SDCard core
UCSBarchlab/PyRTL
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
rggen/rggen
Code generation tool for control and status registers
tpoikela/uvm-python
UVM 1.2 port to Python
steveicarus/iverilog
Icarus Verilog
rdiez/jtag_dpi
JTAG DPI module for OpenRISC simulation with Verilator
fjullien/jtag_vpi
TCP/IP controlled VPI JTAG Interface.
pulp-platform/jtag_dpi
JTAG DPI module for SystemVerilog RTL simulations
stnolting/neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
pyuvm/pyuvm
The UVM written in Python
agra-uni-bremen/crave
Constrained random stimuli generation for C++ and SystemC
verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
trusster/trusster
Hardware Verification library for C++, SystemC and SystemVerilog
mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
drom/awesome-hdl
Hardware Description Languages
microsoft/vscode
Visual Studio Code
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
YosysHQ/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
GeezerGeek/open_sld
Direct Python interface to Altera SLD Mega-function
embox/embox
Modular and configurable OS for embedded applications
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.