littleblank

littleblank's Stars

• caddyserver/caddy

  Fast and extensible multi-platform HTTP/1-2-3 web server with automatic HTTPS

  Language:Go55.5k8303.9k3.9k

• PKUanonym/REKCARC-TSC-UHT

  清华大学计算机系课程攻略 Guidance for courses in Department of Computer Science and Technology, Tsinghua University

  Language:HTML32.7k886317.6k

• MathewSachin/Captura

  Capture Screen, Audio, Cursor, Mouse Clicks and Keystrokes

  Language:C#9.5k2282901.8k

• vosen/ZLUDA

  CUDA on AMD GPUs

  Language:Rust8.3k119150487

• unicorn-engine/unicorn

  Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

  Language:C7.3k2121k1.3k

• 0voice/expert_readed_books

  2021年最新总结，推荐工程师合适读本，计算机科学，软件技术，创业，**类，数学类，人物传记书籍

  6.1k146102.1k

• peng-zhihui/HDMI-PI

  我设计的一个HDMI转MIPI模块，可以用于驱动各种手机屏幕当显示器用。

  Language:C5.7k13548856

• ejoy/ant

  Ant game engine

  Language:Lua3.7k6560372

• weaiken/ebook

  classic books of computer science!

  1.3k262617

• LordNoteworthy/cpu-internals

  Intel / AMD CPU Internals

  Language:C1k471185

• riscvarchive/riscv-cores-list

  RISC-V Cores, SoC platforms and SoCs

  801584205

• GPUOpen-LibrariesAndSDKs/AMF

  The Advanced Media Framework (AMF) SDK provides developers with optimal access to AMD devices for multimedia processing

  Language:C++58462455149

• codec2021/video_codec_learn

  关于视频编解码学习资料

  Language:Python36252105

• labgrid-project/labgrid

  embedded systems control library for development, testing and installation

  Language:Python31231292162

• XUANTIE-RV/openc906

  OpenXuantie - OpenC906 Core

  Language:Verilog296221491

• openasic-org/xkISP

  xkISP：Xinkai ISP IP Core (HLS)

  Language:Verilog22116998

• ZipCPU/openarty

  An Open Source configuration of the Arty platform

  Language:Verilog11714324

• foo86/dcadec

  DTS Coherent Acoustics decoder with support for HD extensions

  Language:C115284040

• ZipCPU/cordic

  A series of CORDIC related projects

  Language:C++8111220

• freecores/ethmac

  Ethernet MAC 10/100 Mbps

  Language:Verilog757232

• risclite/ARM9-compatible-soft-CPU-core

  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

  Language:Verilog695231

• seanliang/HighlightWords

  A Sublime Text 2 & 3 plugin for highlighting mutiple words in different colors

  Language:Python5742421

• adsc-hls/synthesizable_h264

  A Synthesizable implementation of H.264 Video Decoding

  Language:C281205

• openasic-org/xk264

  xk264：AVC/H.264 Video Encoder IP Core (RTL)

  Language:Verilog24418

• darealshinji/dcaenc

  dcaenc is an open-source implementation of the DTS Coherent Acoustics lossy audio codec (by Alexander E. Patrakov; personal mirror)

  Language:C204013

• bobwenstudy/test_kconfig_system

  测试Kconfig系统

  Language:Python116

• Arieswithme/BLE_sample_data_transmit_core5.3

  以2021年7月更新的蓝牙5.3规范为标准，使用Verilog HDL硬件描述语言设计了具有链路层发送数据处理功能的模块。设计方法是：首先根据比特流处理的步骤设计相应的CRC、白化和编码映射等功能模块，然后根据蓝牙发送报文的不同结构设计状态机控制整体发送数据处理的过程。此模块可用Modelsim功能仿真对其进行验证（在代码的testbench里使用了core5.3提供的sample data）。

  Language:Verilog31

• jk4837/ShowDefinitionEx

  A sublime plugin for visually showing definition

  Language:Python34

• risclite/riscv-cores-list

  RISC-V Cores, SoC platforms and SoCs

  3201

• apachecn-archive/huazhang-math-book

  1