liusw-v

Pinned Repositories

axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
Language:SystemVerilog00
CHARM
CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture (Full Paper accepted to FPGA2023!)
Language:C++00
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog00
gemm_hls
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
Language:C++00
High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
Language:HTML00
image-store
00
LC-3
An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".
Language:VHDL00
low-pass-filter
00
PyTorch-Pretrained-ViT
Vision Transformer (ViT) in PyTorch
Language:Python00
SkrSkr
The second place winner for DAC-SDC 2020
Language:Tcl00

liusw-v's Repositories

liusw-v/zipcpu
A small, light weight, RISC CPU soft core
liusw-v/High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
Language:HTML
liusw-v/transformer_core
a student trainning project for HLS and transformer
Language:C++
liusw-v/SkrSkr
The second place winner for DAC-SDC 2020
Language:Tcl
liusw-v/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
liusw-v/CHARM
CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture (Full Paper accepted to FPGA2023!)
liusw-v/ViTCoD
[HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design
Language:Python
liusw-v/image-store
liusw-v/axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
Language:SystemVerilog
liusw-v/SkyNet
liusw-v/trans-fat
An FPGA Accelerator for Transformer Inference
liusw-v/gemm_hls
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
liusw-v/PyTorch-Pretrained-ViT
Vision Transformer (ViT) in PyTorch
liusw-v/WISLearning
liusw-v/low-pass-filter
liusw-v/LC-3
An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".