Pinned Repositories
MSD-FCCM23
Open-source of MSD framework
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
butterfly
Butterfly matrix multiplication in PyTorch
FPGA-Devcloud
Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official Intel® FPGA Devcloud website:
hls4ml
Machine learning on FPGAs using HLS
MIPI_VA-Model
Sigma-Delta-ADC
lloo099's Repositories
lloo099/Sigma-Delta-ADC
lloo099/MIPI_VA-Model
lloo099/Neural-Networks-on-Silicon
This is a collection of works on neural networks and neural accelerators.
lloo099/AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
lloo099/bnn-fpga
Binarized Convolutional Neural Networks on Software-Programmable FPGAs
lloo099/ccxt
A JavaScript / Python / PHP cryptocurrency trading API with support for more than 120 bitcoin/altcoin exchanges
lloo099/CoDeNet
[FPGA'21] CoDeNet is an efficient object detection model on PyTorch, with SOTA performance on VOC and COCO based on CenterNet and Co-Designed deformable convolution.
lloo099/CoDeNet-1
Algorithm-hardware Co-design for Deformable Convolution
lloo099/CoDeNet-2
lloo099/digital-flow
This is a tutorial on standard digital design flow
lloo099/dl_accelerator
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
lloo099/dnn-kernel-fpga
A project for self-implementation of deep learning on FPGAs
lloo099/GNN-ARCH
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
lloo099/GraphACT
[FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms"
lloo099/hardware-aware-transformers
[ACL 2020] HAT: Hardware-Aware Transformers for Efficient Natural Language Processing
lloo099/lpcv2020-hku
Volunteer to search "good" network architectures for Xilinx DPUs
lloo099/matrix_multiplications
Vitis 2020.1 Acceleration Examples and Developed Large Size Matrix Multiplication Examples
lloo099/ml-suite
Getting Started with Xilinx ML Suite
lloo099/MobileNet-V2-inference-HLS
Codes to implement MobileNet V2 in a FPGA
lloo099/NB-Scope
Hardware and software design for NB-Scope.
lloo099/PYNQ_Workshop
lloo099/QNN-MO-PYNQ
lloo099/ResNet50-PYNQ
Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
lloo099/ShiftAddNet
[NeurIPS 2020] ShiftAddNet: A Hardware-Inspired Deep Network
lloo099/trace-ark-trades
Record all purchases and sales made by ARK Invest from 11/12/2019 to the present and visualize these trades via TradingView
lloo099/ultra_net
FPGA-based neural network inference project for 2020 DAC System Design Contest
lloo099/Vitis_with_100Gbps_TCP-IP
100 Gbps TCP/IP stack for Vitis shells
lloo099/vnpy
基于Python的开源量化交易平台开发框架
lloo099/Weekly_Review_in_NTU
The weekly reviews.
lloo099/xup_vitis_network_example
Vitis Network Examples