Pinned Repositories
MSD-FCCM23
Open-source of MSD framework
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
butterfly
Butterfly matrix multiplication in PyTorch
FPGA-Devcloud
Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official Intel® FPGA Devcloud website:
hls4ml
Machine learning on FPGAs using HLS
MIPI_VA-Model
Sigma-Delta-ADC
lloo099's Repositories
lloo099/AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
lloo099/mipi_dsi_bridge_fpga
Source code of MIPI DSI Bridge Published on https://www.circuitvalley.com
lloo099/Vision-FPGA-SoM
tinyVision.ai Vision & Sensor FPGA System on Module
lloo099/2018-DAC-System-Design-Contest
lloo099/Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
lloo099/assign1
lloo099/Binary-Convolutional-Neural-Network-Inference-on-GPU
GPU implementation of Xnor network on inference level.
lloo099/BNN
HLS code for a BNN accelerator
lloo099/BNN-PYNQ
Quantized Neural Networks (QNNs) on PYNQ
lloo099/chai-fpga
Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures
lloo099/CHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
lloo099/Courses-
Quiz & Assignment of Coursera
lloo099/DAC2018-TGIIF
The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track
lloo099/dac_sdc_2020_designs
Designs for finalist teams of the DAC System Design Contest
lloo099/DeepBurning
Automatic generation of FPGA-based learning accelerators for the neural network family
lloo099/Demo_qr
lloo099/DiracDeltaNet
PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
lloo099/dnnweaver2
Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
lloo099/EyerissSimulator
Eyeriss chip simulator
lloo099/gemmbitserial
Fast matrix multiplication for few-bit integer matrices on CPUs.
lloo099/gemx
Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
lloo099/IBM_Capstone_Project
lloo099/nitro-parts-lib-mipi
RTL for mipi serialize and deserialize
lloo099/Quantized_Resnet_FPGA
8bit-quantized convolution module
lloo099/ReBNet
Residual Binarized Neural Network
lloo099/RFNoC-HLS-NeuralNet
lloo099/rip
lloo099/systolic-array
HLS implemented systolic array structure
lloo099/VecQ
lloo099/XNOR-Net
ImageNet classification using binary Convolutional Neural Networks