lomano77

lomano77's Stars

• bitwarden/android

  Bitwarden mobile app for Android.

  Language:Kotlin6.2k1401.6k786

• steveicarus/iverilog

  Icarus Verilog

  Language:C++2.8k135707519

• nigels-com/glew

  The OpenGL Extension Wrangler Library

  Language:C2.6k143262614

• airbus-seclab/qemu_blog

  A series of posts about QEMU internals:

  1.3k455141

• VerticalResearchGroup/miaow

  An open source GPU based off of the AMD Southern Islands ISA.

  Language:Verilog1k14416235

• leecher1337/ntvdmx64

  Run Microsoft Windows NTVDM (DOS) on 64bit Editions

  Language:C7934225381

• p7zip-project/p7zip

  A new p7zip fork with additional codecs and improvements (forked from https://sourceforge.net/projects/sevenzip/ AND https://sourceforge.net/projects/p7zip/).

  Language:C77820126108

• umanovskis/baremetal-arm

  An ebook about bare-metal programming for ARM

  Language:C6212714130

• ARM-software/CMSIS_4

  Cortex Microcontroller Software Interface Standard (V4 no longer maintained)

  Language:C452560400

• adki/AMBA_AXI_AHB_APB

  AMBA bus lecture material

  Language:Verilog36280125

• Xilinx/qemu

  Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

  Language:C2383676151

• davidepatti/noxim

  Network on Chip Simulator

  Language:C++22517140120

• tukl-msd/DRAMSys

  DRAMSys a SystemC TLM-2.0 based DRAM simulator.

  Language:C++199154752

• adki/gen_amba_2021

  AMBA bus generator including AXI4, AXI3, AHB, and APB

  Language:C1663442

• ashwio/arm64-hypervisor-tutorial

  Language:Assembly9516324

• adki/gen_amba

  AMBA bus generator including AXI, AHB, and APB

  Language:C874437

• snbk001/Verilog-Design-Examples

  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

  Language:Verilog871015

• zero-day-labs/riscv-iommu

  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

  Language:SystemVerilog7052714

• adki/DPI_Tutorial

  SystemVerilog Direct Programming Interface (DPI) Tutorial

  Language:C422022

• quic/qbox

  Qbox

  Language:C++31697

• adki/cosim_bfm_library

  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI

  Language:C274011

• ic-lab-duth/NoCpad

  HLS for Networks-on-Chip

  Language:C++27615

• adki/RTL-Design-For-FPGA

  Engineering Program on RTL Design for FPGA Accelerator

  Language:VHDL262010

• leds-lab/redscarf

  System-on-Chip Interconnection Network - Simulation Environment (front-end)

  Language:C++14320

• adki/Deep_Learning_Blocks

  DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep learning inference network.

  Language:C12107

• AcornPublishing/tls-cryptography

  TLS 구현으로 배우는 암호학 [C++로 만드는 HTTPS 서비스]

  Language:C++72

• adki/network_vpi_lib

  Network VPI Library is a collection of VPI (Verilog Programming Interface) tasks that handles network packets, which include Ethernet, IP, UDP, TCP and PTPv2.

  Language:C7102

• adki/DLR_Projects

  Deep learning projects using DLR (Deep Learning Routines)

  Language:C6302

• adki/HiPi-Bus_shared_bus_protocol

  The HiPi+Bus (하이파이플러스버스) is a shared bus with pipelined protocol supporting multi-cache coherency.

  Language:TeX420

• adki/RACE_protocol

  RACE Protocol: Remote Access Cache Coherency Enforcement Protocol

  420