lucabertaccini

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

dummy_vip

Files for the IP Integration Exercise

flexfloat

C library for the emulation of reduced-precision floating point types

fpnew

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

pulp-dsp

pulp_soc

Spoon-Knife

This repo is for demonstration purposes only.

tristan-unified-access-page

Unified Access Page for the TRISTAN project

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

lucabertaccini/cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

lucabertaccini/dummy_vip

Files for the IP Integration Exercise

lucabertaccini/flexfloat

C library for the emulation of reduced-precision floating point types

lucabertaccini/fpnew

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

lucabertaccini/pulp-dsp

lucabertaccini/pulp_soc

lucabertaccini/Spoon-Knife

This repo is for demonstration purposes only.

lucabertaccini/tristan-unified-access-page

Unified Access Page for the TRISTAN project