Pinned Repositories
2019-Electronic-Design-Competition-D-Question-Based-On-FPGA-and-Verilog
2019-TI-Electronic-Design-Competition
2019 TI杯全国大学生电子设计大赛
2021-Electronic-Design-Competetion-Analog-Digital-Wireless
2021全国大学生电子设计大赛E题:数字-模拟信号混合传输收发机
Basic-FPGA-Driver
FPGA驱动一些模块的Verilog代码
cm3-bd
cortexm3 design start with vivado block design
CourseSelection-Weixin-APP
微信小程序选课系统
Cpp-Primer-Plus
C++ Primer Plus 6th Answers
lyjslay.github.io
Robomaster-2020-Tars-Go-Vision
2020年ICRA Robomaster挑战赛Tars-Go战队视觉算法
TodoSync
基于 GitHub Actions 的定时任务，将 Canvas LMS 的作业、测验、公告、讨论、全局通知同步到 Microsoft Todo
lyjslay's Repositories
lyjslay/CourseSelection-Weixin-APP
微信小程序选课系统
lyjslay/2021-Electronic-Design-Competetion-Analog-Digital-Wireless
2021全国大学生电子设计大赛E题:数字-模拟信号混合传输收发机
lyjslay/Robomaster-2020-Tars-Go-Vision
2020年ICRA Robomaster挑战赛Tars-Go战队视觉算法
lyjslay/lyjslay.github.io
lyjslay/2019-Electronic-Design-Competition-D-Question-Based-On-FPGA-and-Verilog
lyjslay/2019-TI-Electronic-Design-Competition
2019 TI杯全国大学生电子设计大赛
lyjslay/Basic-FPGA-Driver
FPGA驱动一些模块的Verilog代码
lyjslay/TodoSync
基于 GitHub Actions 的定时任务，将 Canvas LMS 的作业、测验、公告、讨论、全局通知同步到 Microsoft Todo
lyjslay/cm3-bd
cortexm3 design start with vivado block design
lyjslay/Cpp-Primer-Plus
C++ Primer Plus 6th Answers
lyjslay/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
lyjslay/Deep-Learning-Papers-Reading-Roadmap
Deep Learning papers reading roadmap for anyone who are eager to learn this amazing tech!
lyjslay/hw
RTL, Cmodel, and testbench for NVDLA
lyjslay/JLU-EE-template
吉林大学电子科学与工程学院毕业论文(设计)模板
lyjslay/TensorRT_Tutorial
lyjslay/tinyriscv
A very simple and easy to understand RISC-V core.
lyjslay/verilog-axis
Verilog AXI stream components for FPGA implementation
lyjslay/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation