maheshbhatk
Interested in VLSI Domain. Coding in Verilog, Python, TCL. Physical Design!!!
United States
Pinned Repositories
16EC7G4
VLSI Testing for ICs
APB_Bridge
asap
Implementation of ASAP algorithm to a CSV file
ATPG_Tool_with-UI
Creating a end to end Open source Tool. Runs ATPG Algorithm(PODEM), Testablilty measures(SCOAP Analysis) for the Circuit created by user in Graphical User Interface
i2c
The several codes i have seen so far uses sequential execution of the scl and sda and therefore sda changes when scl is at the edge.But in my code the sda changes only when scl is exactly at zero(Like the actual waveform of the I2C protocol)
i2c_master_slave
Both read and write operation
mytools
Trying to learn new tools
RTL_to_GDSII_Adder
RTL to GDSII of a 64bit Adder
Single_Cycle_Processor
A single cycle CPU has been constructed in Verilog.
spi
SPI Master and SPI Slave
maheshbhatk's Repositories
maheshbhatk/spi
SPI Master and SPI Slave
maheshbhatk/APB_Bridge
maheshbhatk/ATPG_Tool_with-UI
Creating a end to end Open source Tool. Runs ATPG Algorithm(PODEM), Testablilty measures(SCOAP Analysis) for the Circuit created by user in Graphical User Interface
maheshbhatk/i2c_master_slave
Both read and write operation
maheshbhatk/16EC7G4
VLSI Testing for ICs
maheshbhatk/asap
Implementation of ASAP algorithm to a CSV file
maheshbhatk/covid-vaccine-booking
This very basic script can be used to automate COVID-19 vaccination slot booking on India's Co-WIN Platform. SET FOR BENGALURU
maheshbhatk/i2c
The several codes i have seen so far uses sequential execution of the scl and sda and therefore sda changes when scl is at the edge.But in my code the sda changes only when scl is exactly at zero(Like the actual waveform of the I2C protocol)
maheshbhatk/mytools
Trying to learn new tools
maheshbhatk/RTL_to_GDSII_Adder
RTL to GDSII of a 64bit Adder
maheshbhatk/Single_Cycle_Processor
A single cycle CPU has been constructed in Verilog.
maheshbhatk/DNS-using-Cisco-Packet-Tracer
DNS implementation using Cisco Packet Tracer Software in various configurations.
maheshbhatk/dvsd-12-Bit_Adder_Using_4-Bit_CLA
Designing a 12 Bit adder using 4 Bit CLA
maheshbhatk/maheshbhatk.github.io
maheshbhatk/RealTimeClock
Real Time Clock(RTC) on 7-segment display.Implementation on FPGA
maheshbhatk/RTL_Practice
Very simple basics using Verilog
maheshbhatk/UART
UART in Verilog.