maheshbhatk/dvsd-12-Bit_Adder_Using_4-Bit_CLA

Designing a 12 Bit adder using 4 Bit CLA

dvsd-12-Bit_Adder_Using_4-Bit_CLA

This work is to prodece a clean GDS required to print photomasks used for the fabrication of 12-Bit Adder using CLA logic in SkyWater 130 nm PDK.

Design Overview

IP specs provided

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. For more information check GitHub Pages.

OpenLane design stages

1. Synthesis
   • yosys - Performs RTL synthesis
   • abc - Performs technology mapping
   • OpenSTA - Performs static timing analysis on the resulting netlist to generate timing reports
2. Floorplan and PDN
   • init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
   • ioplacer - Places the macro input and output ports
   • pdn - Generates the power distribution network
   • tapcell - Inserts welltap and decap cells in the floorplan
3. Placement
   • RePLace - Performs global placement
   • Resizer - Performs optional optimizations on the design
   • OpenDP - Perfroms detailed placement to legalize the globally placed components
4. CTS
   • TritonCTS - Synthesizes the clock distribution network (the clock tree)
5. Routing
   • FastRoute - Performs global routing to generate a guide file for the detailed router
   • CU-GR - Another option for performing global routing.
   • TritonRoute - Performs detailed routing
   • SPEF-Extractor - Performs SPEF extraction
6. GDSII Generation
   • Magic - Streams out the final GDSII layout file from the routed def
   • Klayout - Streams out the final GDSII layout file from the routed def as a back-up
7. Checks
   • Magic - Performs DRC Checks & Antenna Checks
   • Klayout - Performs DRC Checks
   • Netgen - Performs LVS Checks
   • CVC - Performs Circuit Validity Checks

Installation

Prerequisites

• Preferred Ubuntu OS)
• Docker 19.03.12+
• GNU Make
• Python 3.6+ with PIP
• Click, Pyyaml: pip3 install pyyaml click

Run the following commands to Install Openlane

• git clone https://github.com/The-OpenROAD-Project/OpenLane.git

• cd OpenLane/

• make openlane

• make pdk

• make test # This a ~5 minute test that verifies that the flow and the pdk were properly installed

Running OpenLane

Use the command - make mount

Use the following example to check the overall setup:

./flow.tcl -design spm

To run openlane in interactive mode

./flow.tcl -interactive

Pre-layout

Simulation

Terminal snap (To perform pre-layout simulation)

GTKWave Output Waveform

Synthesis

• In our design, Run - flow.tcl -design dvsd_adder_12bit -src my/dvsd_adder_12bit.v -init_design_config

Make the Required changes in the generated .config.tcl and Run

flow.tcl -design dvsd_adder_12bit -tag first_run

Synthesis Reports

Yosys synthesis strategies

Floorplanning

• Settings in Config.tcl File

• Floorplan View

Placement

• Placement Analysis

• Routing Resources Analysis

• Final Congestion Report

• Complete Detail Routing

• Placement View

Layout

• Closer View of the Final Layout Design

Layout vs Schematic

• Subcircuit Summary

• Subcircuits Pins

Final Summary