mailtomaxxwell's Stars
tbrown122387/r_and_python_book
tenstorrent/pytorch2.0_ttnn
⭐️ TTNN Compiler for PyTorch 2.0 ⭐️ It enables running PyTorch2.0 models on Tenstorrent hardware
LTRData/ImDisk
ImDisk Virtual Disk Driver
tuxera/reliance-edge
Transactional power-failsafe filesystem for microcontrollers
tuxera/ntfs-3g
NTFS-3G Safe Read/Write NTFS Driver
vllm-project/vllm
A high-throughput and memory-efficient inference and serving engine for LLMs
exo-explore/exo
Run your own AI cluster at home with everyday devices 📱💻 🖥️⌚
Xilinx/llvm-aie
Fork of LLVM to support AMD AIEngine processors
tsengs0/ECC_Hardware
Hardware implementation of Error-Correction Code in Verilog
pansygrass/ecc
Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrated Circuits.
kgpai94/ECC-Encryption-System
This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a spartan 3 FPGA kit.
alanjian85/raster-i
A hardware rasterizer created for real-time rendering
ncsu-eda/FreePDK3
physical-computation/sunflower-embedded-system-emulator
Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.
chillancezen/Zelda.RISCV.Emulator
A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux
RinHizakura/riscv-emulator
A project for learning RISC-V architecture purpose
lupyuen/nuttx-star64
Apache NuttX RTOS for Pine64 Star64 64-bit RISC-V SBC (StarFive JH7110)
rvkrypto/rvkrypto-fips
[HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension
mdepx/mdepx
MDX — A BSD-style RTOS
IARSystems/iar-risc-v-gd32v-eval
Example projects for the IAR RISC-V GD32V Evaluation board in IAR Embedded Workbench for RISC-V
lupyuen/tcc-riscv32-wasm
TCC (Tiny C Compiler) for 64-bit RISC-V, compiled to WebAssembly with Zig Compiler
64kramsystem/qemu-pinning
My QEMU fork with pinning (affinity) support and a few tweaks.
rockcarry/ffvm
a riscv32 rv32imc emulator written in c.
ghent360/riscvOnColorlight-5A-75B
RISC-V soft core running on Colorlight 5B-74B.
vshymanskyy/interp
Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining
ring00/bbl-ucore
uCore OS Labs on Berkeley bootloader
vllogic/openocd_cmsis-dap_v2
支持CMSIS-DAP v2接口协议,支持ARM、RISCV、ESP32等目标芯片,详见Wiki及release
jnaulet/OpenPicoRTOS
Very small, safe, lightning fast, yet portable preemptive RTOS with SMP support
splinedrive/lets_build_a_compiler_for_riscv
A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
IBM/rocc-software
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)