AFU framework for streaming applications with CAPI connected FGPAs.
More info
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Webinar: https://ieee-isto.webex.com/ieee-isto/lsr.php?RCID=4eb9bafd1a3f4ebfa1fb8ee1835eab39
Unfortunately, the webinar was automatically removed. I'm not sure if it can be recovered.
Please note the following;
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It is recommended to read the CAPI Users Guide before using this framework.
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For now there is very limited instructions and documentation, but this will all be added later. An example project file for the Nallatech P385-A7 card with the Altera Stratix V GX A7 FPGA will also be added later. The current Computing Unit (CU) implements a simple memcpy function.
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This framework runs in dedicated mode and was developed to be used with Linux.
This will be added later.
accelerator
lib
- VHDL global packagesfunctions.vhd
- Helper functionspsl.vhd
- PSL constants and interface recordswed.vhd
- WED record and parse procedure
pkg
- VHDL packagesrtl
- VHDL architecturesafu.vhd
- PSL to AFU wrappercontrol.vhd
- Framework controlcu.vhd
- Computing Unit - implements the actual AFU functionalitydma.vhd
- Direct Memory Accessfifo.vhd
- First-In-First-Outframe.vhd
- AFU top levelmmio.vhd
- Memory-Mapped-Input-Outputram.vhd
- Random-Access-Memory
host
app
- Host application sources
sim
pslse
- PSL Simulation Engine sourcespslse.parms
- PSLSE parameter filepslse_server.dat
- PSLSE server used by the host application to attachshim_host.dat
- Simulation host used by the PSLSEvsim.tcl
- Compilation and simulation script for vsimwave.do
- Wave script for vsim
Makefile
- Global makefile
This will be added later.
The Computing Unit (CU) implements the actual function of the AFU.
The dma_package
defines a number of procedures that can be used to communicate with the DMA. They will be updated soon to match the specifications in the slides.
The following instructions target ModelSim (vsim).
Starting from release 15.0 of Quartus II, the included ModelSim-Altera Starter Edition (free) has mixed-language support, which is required for simulation of this framework with the current PSLSE.
It is assumed that the 32-bit version of vsim is installed in /opt/altera/15.0/modelsim_ase/
and /opt/altera/15.0/modelsim_ase/bin
is added to your PATH.
Please note that all listed make
commands should be executed from the root of this project.
- Clone the repository. enter the directory and initialize the submodules
git clone https://github.com/mbrobbel/capi-streaming-framework.git
cd capi-streaming-framework
git submodule update --init
- Set your
VPI_USER_H_DIR
environment variable to point to theinclude
directory of your simulator e.g.:
export VPI_USER_H_DIR=/opt/altera/15.0/modelsim_ase/include
- Build the
PSLSE
:
make pslse-build
This will build the PSLSE with the DEBUG flag and the AFU driver for a 32-bit simulator.
- Build the host application for simulation:
make sim-build
- Start the simulator:
make vsim-run
This will start vsim and execute the vsim.tcl
script, which will automatically compile the sources.
- Start simulation:
Use the following command in the vsim console to start the simulation.
s
- Open a new terminal and start the PSLSE:
make pslse-run
- Open a new terminal and run your host application. This will run your host application from the
sim
directory:
make sim-run ARGS="<number-of-cachelines-to-copy>"
- Wait for your host application to terminate then switch to the PSLSE terminal and kill (
CTRL+C
) the running PSLSE process to inspect the wave.
During development vsim
can be kept running.
The vsim.tcl
script also allows to quickly run the following commands again from the vsim
console:
r
- Recompile theHDL
source filess
- Start the simulationrs
- Recompile theHDL
source files and restart the simulation
This will be added later. A timing issue needs to be resolved first.