/Advanced-Physical-Design-using-OpenLane-Sky130

  1. Day1 – Inception of open-source EDA, OpenLANE and Sky130 PDK

  • How to talk to computers
  • SoC design and OpenLANE
  • Starting RISC-V SoC Reference design
  • Get familiar to open-source EDA tools

  1. Day 2 - Understand importance of good floorplan vs bad floorplan and introduction to library cells

  • Chip Floor planning considerations
  • Library Binding and Placement
  • Cell design and characterization flows
  • General timing characterization parameters

  1. Day 3 - Design and characterize one library cell using Magic Layout tool and ngspice

  • Labs for CMOS inverter ngspice simulations
  • Inception of Layout – CMOS fabrication process Sky130 Tech File Labs

  1. Day 4 - Pre-layout timing analysis and importance of good clock tree

  • Timing modelling using delay tables
  • Timing analysis with ideal clocks using openSTA
  • Clock tree synthesis TritonCTS and signal integrity
  • Timing analysis with real clocks using openSTA

  1. Day 5 - Final steps for RTL2GDS

  • Routing and design rule check (DRC)
  • PNR interactive flow tutorial

  1. Day1 – Inception of open-source EDA, OpenLANE and Sky130 PDK

Fig.1 This is the terminal window.

Fig.2 In the terminal window being in tools diretory do "ls" to list the files and folders.

In the fig.2 we can see two folders.
  1. openlane
  2. pdks

To Launch the tool


Fig.3, to launch the openlane type the command "make mount"

Types of PDKs(Process Design Kit)

Fig.4 It shows the 3 types of PDKs

In the figure 4 it seen that there three types of pdks
  1. skywater-pdk
  2. open-pdks
  3. sky130A

PDK used in this Lab is sky130A

This sky130A pdk contains libs.tech, and libs.ref


Fig.5 It shows the contents of sky130A and libs.tech


Fig.6 It shows the contents of libs.ref

The library used from the sky130A pdk is sky130_fd_sc_hd

Fig.7 It shows the contents of sky130_fd_sc_hd

The sky130_fd_sc_hd contains various process corners, which are shown in the figure below

Fig. 8 Figure shows the various process corners

openlane terminal needs to be launched from being in the openlane directory, which is shown in the figure below


Fig.9 Figure shows oipenlane directory.

From the openlane directory type the command "make mount"


Fig. 10 Figure shows the command "make mount" To start the flow in interactive way type the way shown in the below figure"


Fig.11 Figure shows the command for making the tool interactive.


Fig.12 Figure shows the preparation stage which creates necessary directories.

To run the synthesis



Fig. 13 Figure shows the synthesis command

Fig. 14-a Synthesis Results

Fig. 14-b Synthesis Results




Fig. 14-c Synthesis Results

  1. Day 2 - Understand importance of good floorplan vs bad floorplan and introduction to library cells

To run the floor plan

Fig. 1 Figure shows the command to run the floorplan

Visualize the floorplan done in the magic

Fig. 2 Figure shows the command to visualize the floorplan in the magic tool

Fig. 3 Figure shows complete floorplan of the design picorv32a

Fig. 4 Figure shows the horizontal IO

Fig. 5 Figure shows the vertical IO

Fig. 6 Figure shows the standard cells after floorplan done

To run the placement

Fig. 1 Figure shows the command to run the placement

Fig. 2 Figure shows the command to visualize the placement in the magic tool

Fig. 3 Figure shows placement done in the magic tool

  1. Day 3 - Design and characterize one library cell using Magic Layout tool and ngspice

Fig. 1 Figure shows IO pins setting

Fig. 2 Figure shows the command to run floorplan after setting IO distance

Fig. 3 Figure shows the command to see in the magic tool after fllorplan is done

Fig. 4 Figure shows PINS are not equidistance

Fig. 5 Figure shows the command to open the inverter in the magic tool

Fig. 6 Figure shows the spice netlist generated by the magic tool

Fig. 7 Figure shows the simulation done using ngspice for the inverter design

  1. Day 4 - Pre-layout timing analysis and importance of good clock tree

Fig.1 Figure shows the inverter design in the magic tool

Fig. 2 Figure shows the layout of the design in the magic tool

Fig. 3 Figure shows the grid command, it is for the purpose of creating LEF file

Fig. 4-1 Figure shows the process to convert Labels to Ports

Fig. 4-2 Figure shows the process to convert Labels to Ports

Fig. 5 Command to generate LEF file

Fig. 6 Figure shows editing of the config dot tcl file to run the custom built cells

Fig. 7 Figure shows the required files that are required in the src folder of the design

Fig. 8 Figure shows the design preparation for synthesis and other steps

Fig. 9 Figure shows the placed logic in the magic layout tool

Fig. 10 Figure shows the routed design

Fig. 11 Figure shows our custom cell