Pinned Repositories
adder_test1
Advanced-Physical-Design-using-OpenLane-Sky130
Analog-Design-Modelling
Analog Hardware Hands on Design Labs and Modelling using SPICE Tools (NI Multisim, LTSpice)
approx-fpgas
Approximate arithmetic circuits for FPGAs
Atalanta
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
basic-verilog
caravel_adder_project
https://caravel-user-project.readthedocs.io
caravel_adder_project1
RTLDesignusingVerilogwithSKY130Technology
RTL design using Verilog with SKY130 Technology. This is a 5-Day online workshop conducted by VLSI System Design, Banglore from 26th-30th May 2021. Learn basics of digital design using Verilog language, various RTL coding styles, typical synthesis problems faced by the industry, and how to solve them in Verilog.
vsdopenlaneworkshop
This is about openlane flow for ASIC Design
mdzakirhussain's Repositories
mdzakirhussain/RTLDesignusingVerilogwithSKY130Technology
RTL design using Verilog with SKY130 Technology. This is a 5-Day online workshop conducted by VLSI System Design, Banglore from 26th-30th May 2021. Learn basics of digital design using Verilog language, various RTL coding styles, typical synthesis problems faced by the industry, and how to solve them in Verilog.
mdzakirhussain/adder_test1
mdzakirhussain/Advanced-Physical-Design-using-OpenLane-Sky130
mdzakirhussain/basic-verilog
mdzakirhussain/caravel_adder_project
https://caravel-user-project.readthedocs.io
mdzakirhussain/caravel_adder_project1
mdzakirhussain/demoopenlane
mdzakirhussain/myhdl123
mdzakirhussain/openlane
mdzakirhussain/openlaneinstallation
mdzakirhussain/OpenRoad
This is to explore OpenRoad on GitHub codespaces.
mdzakirhussain/opensourceeda-1
mdzakirhussain/pythnon_learning
mdzakirhussain/sv
mdzakirhussain/sv1
mdzakirhussain/systemverilog
mdzakirhussain/te
mdzakirhussain/test
mdzakirhussain/test123
mdzakirhussain/test1_openlane
mdzakirhussain/test1_vnc
mdzakirhussain/test2_openlane
mdzakirhussain/test456
mdzakirhussain/test_codespaces1
mdzakirhussain/test_desktop_codespaces
mdzakirhussain/test_ha
codespace test
mdzakirhussain/test_hls
mdzakirhussain/try1
mdzakirhussain/try2
mdzakirhussain/verilog_examples123