mdzakirhussain

Pinned Repositories

adder_test1
Language:Verilog0 2 00
Advanced-Physical-Design-using-OpenLane-Sky130
0 2 00
Analog-Design-Modelling
Analog Hardware Hands on Design Labs and Modelling using SPICE Tools (NI Multisim, LTSpice)
00
approx-fpgas
Approximate arithmetic circuits for FPGAs
Language:Verilog0 1 00
Atalanta
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
Language:Verilog0 1 00
basic-verilog
0 2 00
caravel_adder_project
https://caravel-user-project.readthedocs.io
Language:Verilog0 1 00
caravel_adder_project1
Language:Verilog0 2 00
RTLDesignusingVerilogwithSKY130Technology
RTL design using Verilog with SKY130 Technology. This is a 5-Day online workshop conducted by VLSI System Design, Banglore from 26th-30th May 2021. Learn basics of digital design using Verilog language, various RTL coding styles, typical synthesis problems faced by the industry, and how to solve them in Verilog.
2 2 02
vsdopenlaneworkshop
This is about openlane flow for ASIC Design
1 2 00

mdzakirhussain's Repositories

mdzakirhussain/RTLDesignusingVerilogwithSKY130Technology
RTL design using Verilog with SKY130 Technology. This is a 5-Day online workshop conducted by VLSI System Design, Banglore from 26th-30th May 2021. Learn basics of digital design using Verilog language, various RTL coding styles, typical synthesis problems faced by the industry, and how to solve them in Verilog.
2 2 02
mdzakirhussain/adder_test1
Language:Verilog0 2 00
mdzakirhussain/Advanced-Physical-Design-using-OpenLane-Sky130
0 2 00
mdzakirhussain/basic-verilog
0 2 00
mdzakirhussain/caravel_adder_project
https://caravel-user-project.readthedocs.io
Language:Verilog0 1 00
mdzakirhussain/caravel_adder_project1
Language:Verilog0 2 00
mdzakirhussain/demoopenlane
Language:Verilog
mdzakirhussain/myhdl123
mdzakirhussain/openlane
2 0
mdzakirhussain/openlaneinstallation
Language:Shell
mdzakirhussain/OpenRoad
This is to explore OpenRoad on GitHub codespaces.
mdzakirhussain/opensourceeda-1
1
mdzakirhussain/pythnon_learning
2 0
mdzakirhussain/sv
mdzakirhussain/sv1
mdzakirhussain/systemverilog
2 0
mdzakirhussain/te
mdzakirhussain/test
mdzakirhussain/test123
mdzakirhussain/test1_openlane
1
mdzakirhussain/test1_vnc
mdzakirhussain/test2_openlane
Language:Tcl
mdzakirhussain/test456
mdzakirhussain/test_codespaces1
mdzakirhussain/test_desktop_codespaces
mdzakirhussain/test_ha
codespace test
Language:Verilog1
mdzakirhussain/test_hls
Language:Python
mdzakirhussain/try1
Language:Verilog2 0
mdzakirhussain/try2
Language:Verilog
mdzakirhussain/verilog_examples123