Learn basics of digital design using verilog language, various RTL coding styles, typical synthesis problems faced by industry and how to solve them in Verilog

Workshop intends to teach the verilog coding guidelines that results in predictable logic in Silicon. it is important to note that every verilog code is not synthesizable and even if it is , it may result in different logic depending on the coding styles used. The course details all these aspects of the Verilog HDL with theory and backed with lot of practical examples. Workshop introduces to the digital logic design using Verilog HDL . Validating the functionality of the design using Functional Simulation. Writing Test Benches to validate the functionality of the RTL design . Logic synthesis of the Functional RTL Code. Gate Level Simulation of the Synthesized Netlist.

Workshop Day wise Content :

Day 1 - Introduction to Verilog RTL design and Synthesis

Day 2 - Timing libs, hierarchical vs flat synthesis and efficient flop coding styles

Day 3 - Combinational and sequential optmizations

Introduction to optimizations
Combinational logic optimizations
Sequential logic optimizations
Sequential optimzations for unused outputs

Day 4 - GLS, blocking vs non-blocking and Synthesis-Simulation mismatch

GLS, Synthesis-Simulation mismatch and Blocking/Non-blocking statements
Labs on GLS and Synthesis-Simulation Mismatch
Labs on synth-sim mismatch for blocking statement

Day 5 - Optimization in synthesis

If Case constructs
Labs on "Incomplete If Case"
Labs on "Incomplete overlapping Case"
for loop and for generate
Labs on "for loop" and "for generate"

Day 1 - Introduction to Verilog RTL design and Synthesis

Introduction to open-source simulator iverilog

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.

For more Info.

Labs using iverilog and gtkwave

The following are the commands to simulate the design written in the verilog code. Before going to simulation let us understand some terminology, Any design for example let us consider MUX 4x1 is been described in the Verilog HDL such a described file is called design file. Now, the description of the design is correct or not we need to confirm it, that is done through testbench, testbench is also a verilog code only but that consists of majorly two things

Instantiation of the design
Test Vectors

We did the following simulation for Day-1

Mux 2x1

The following commands are used for performing the simulation using iverilog simulator

For compiling the design file(s) and testbench file
iverilog design_file_name.v testbench_file_name.v
After comiling a file with the name and extension a.out will be generated. And this file is executed using the command
vvp a.out
This will generate a file with the extension .vcd, for this file name can be given by the user in the testbench.
And finally to see the waveform we use gtkwave using the coomand
gtkwave filename.vcd

Mux 2x1 Simulation results

Fig.1 Command to compile design file and testbench file is "iverilog good_mux.v tb_good_mux.v"

Fig.2 Command to execute is "./a.out" Fig.3 shows vcd(value change dump) file been generated successfully Fig.4 shows the command to invoke gtkwave using vcd file Fig.5 Finally simulation result

Introduction to Yosys and Logic synthesis

Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Selected features and typical applications:

Process almost any synthesizable Verilog-2005 design
Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
Built-in formal methods for checking properties and equivalence
Mapping to ASIC standard cell libraries (in Liberty File Format)
Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
Foundation and/or front-end for custom flows

What is Logic Synthesis?

Logic synthesis is a process of converting HDL code to gate level information, which is technically called gate-level netlist. To do logic synthesis we use software tool called synthesizer, in our case we are using open-source synthesizer tool called yosys.

Labs using Yosys and Sky130 PDKs

We did the synthesis for the following design on Day-1

Mux 2x1

The following commands and steps are followed for performing the synthesis using yosys synthesizer

First step we have to read standard cells library into the yosys using the command

read_liberty -lib sky130_fd_sc_hd__tt_025C_1v80.lib

Here sky130_fd_sc_hd__tt_025C_1v80.lib is standard cell library which is from skywatertechnology

Second step is to read verilog files into the yosys using the command

read_verilog filename.v

Thrird step is to perform synthesis using the command

synth -top module_name

Fourth step is to map to standard cells using the following command

abc -liberty sky130_fd_sc_hd__tt_025C_1v80.lib

Fifth step is to write out the netlist file using the command

write_verilog your_file_name.v

Mux 2x1 Synthesis results

Fig.1 Invoking yosys

Fig.2 Yosys terminal

Fig.3 Read liberty file

Fig.4 Read verilog file

Fig.5 Run synthesis

Fig.6 After synthesis

Fig.7 Standard cell netlist generation command

Fig.8 After standard cell netlist

Fig.9 Writing out standard cell netlist to a file

Fig.10 Show command to view the diagram of cells

Fig.11 View in Diagram

Day 2 - Timing libs, hierarchical vs flat synthesis and efficient flop coding styles

In the Day 2 of the workshop, we have been given Introduction to what standard cells library means and what it contains. And also about types of synthesis such as differences between hierarchical vs flat synthesis. And, finally we also been given insights on optimization and different coding styles.

We did the simulation on Day-2 for following list

DFF with Asynchronous reset
DFF with synchronous set
DFF with synchronous reset

We did the synthesis for the following list of designs on Day-2

Multi module synthesis using hierarchical and flat approaches
DFF with Asynchronous reset
DFF with synchronous set
DFF with synchronous reset

Introduction to timing .libs

Sample of .lib that is liberty file

Hierarchical vs Flat Synthesis

The following are the images of synthesis showing differences between hierarchical and flat synthesis

Fig.1 Invoke yosys

Fig.2 Yosys terminal

Fig.3 Read liberty

Fig.4 Read verilog

Fig.5 After verilog read

Fig.6 Synth -top for netlist

Fig.7 After synth command

Fig.8 abc command to map to standard cells

Fig.9 Result of hierarchical synthesis

Fig.10 Command for Flatten synthesis

Fig.11 Result of flatten synthesis

Various Flop Coding Styles and optimization

DFF with Asynchronous reset Simulation results

Fig.1 compile design file and testbench file

Fig.2 execute "./a.out"

Fig.3 shows vcd(value change dump) file been generated successfully

Fig.4 shows the command to invoke gtkwave using vcd file

Fig.5 Finally simulation result

DFF with Asynchronous set Simulation results

Fig.1 compile design file and testbench file

Fig.2 execute "./a.out"

Fig.3 shows the command to invoke gtkwave using vcd file

Fig.4 Finally simulation result

DFF with synchronous reset Simulation results

Fig.1 compile design file and testbench file

Fig.2 execute "./a.out"

Fig.3 shows the command to invoke gtkwave using vcd file

Fig.4 Finally simulation result

Day 3 - Combinational and sequential optimizations

Introduction to optimizations
Combinational logic optimizations
Sequential logic optimizations
Sequential optimzations for unused outputs

Introduction to optimizations

In day 3 we have been given various examples on how do synthesizer tool will optimize the designs done in RTL for combinational and sequential designs. Most optimized logic is efficient in terms of area and power saving.