mgottscho

availability-aware-matlab-charging-postprocess

MATLAB post-processing code for battery charging-aware power management experiments

availability-aware-mbed-aux

availability-aware-mbed-HardwareTickerLib

availability-aware-mbed-HardwareTimersLib

availability-aware-mbed-master

availability-aware-mbed-power-burner

availability-aware-mbed-power-measurement

availability-aware-mbed-sensor-unit-tests

X-Mem

Extensible Memory Benchmarking Tool

bedrock-rtl

High quality and composable base RTL libraries in SystemVerilog

mgottscho/availability-aware-matlab-charging-postprocess

MATLAB post-processing code for battery charging-aware power management experiments

mgottscho/availability-aware-mbed-aux

mgottscho/availability-aware-mbed-master

mgottscho/availability-aware-mbed-power-burner

mgottscho/availability-aware-userdata-processing

scripts to process Cambridge DeviceAnalyzer dataset

mgottscho/bedrock-rtl

High quality and composable base RTL libraries in Verilog

mgottscho/dpcs-cacti65

Modified version of CACTI 6.5 to model necessary features of DPCS

mgottscho/dpcs-fault-map-generation

MATLAB code to synthesize SRAM cache fault maps at different voltages

mgottscho/dpcs-gem5

Modified gem5 simulator to implement Dynamic Power/Capacity Scaling (DPCS)

mgottscho/dpcs-ibm45soi-spice

SPICE simulations of SRAM cells for the DPCS project

mgottscho/dpcs-sram-noisemargin-analysis

MATLAB code to postprocess SRAM SPICE data for noise margins with process variability

mgottscho/eccgrp-data-stats

Some MATLAB code for computing data transitions in a memory trace

mgottscho/eccgrp-periodic-file-dumper

Shell code for periodically dumping contents of a file

mgottscho/fault-tolerant-spm

fault tolerant scratchpad

mgottscho/performability-matlab-models

MATLAB code that implements performability models (theoretical app performance in presence of corrected memory errors)

mgottscho/rooflining-util

Simple Python and Jupyter utilities for analytical rooflining studies

mgottscho/sdecc-gem5-stable-50ff05095970

Branch of a specific gem5 commit used for RISC-V stuff and memory content tracing extensions for the SDECC project

mgottscho/sdecc-penaltybox-rtl

Verilog RTL for the Software-Defined ECC (SDECC) Penalty Box

mgottscho/sdecc-viffto-alpha-isa-decoder

C++ implementation of the Alpha ISA decoder based on hacked code from gem5. Used for SDECC and ViFFTo projects

mgottscho/sdecc-viffto-app-demo

Hello World example program for interacting with the SDELC embedded C library for implementing application-defined memory DUE handlers

mgottscho/sdecc-viffto-ecc-ctrl

Primary development repository for all ECC encoding, decoding, heuristic recovery, etc. for SDECC and ViFFTo/SDELC projects

mgottscho/sdecc-viffto-isa-sparsity

MATLAB code for exhaustively checking all possible 32-bit words to see what fraction are legal instructions for RISC-V, MIPS, and Alpha ISAs

mgottscho/sdecc-viffto-memory-due-userspace-handler

Userspace C library for allowing applications to directly handle detected-but-uncorrectable errors (DUEs) in memory for the Software-Defined ECC (SDECC) and ViFFTo/SDELC projects

mgottscho/sdecc-viffto-mips-isa-decoder

C++ implementation of the MIPS32 ISA decoder for command-line and MATLAB usage for the SDECC and ViFFTo projects

mgottscho/sdecc-viffto-riscv-isa-decoder

C++ implementation of a RISC-V instruction decoder for use on the command-line and in MATLAB, for the SDECC and ViFFTo projects

mgottscho/sdecc-viffto-riscv-isa-sim

Modified version of the RISC-V Spike reference ISA simulator to support memory data tracing and fault injection for the Software-Defined ECC and ViFFTo projects -- checkout sdecc branch

mgottscho/sdecc-viffto-riscv-pk

RISC-V Proxy Kernel -- modified for the Software-Defined ECC (SDECC) and ViFFTo projects -- check out the sdecc branch

mgottscho/Triton-Puzzles

Puzzles for learning Triton (my solution)

mgottscho/verible-py

python3/pip3 wrapper for installing verible

mgottscho/X-Mem

the eXtensible MEMory characterization tool