Pinned Repositories
cdl_hardware
CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc
cparserlibfirm_riscv32
cproc
C11 compiler (mirror)
cproc_riscv32
elftools_riscv32
assembler and linker for riscv32
pyhdlsim
pyocdriscv32
Python script for controlling the debug-jtag port of riscv cores
qbe_riscv32
riscv32_beluga
c compiler beluga with riscv32 backend
riscv32_lcc
michg's Repositories
michg/pyocdriscv32
Python script for controlling the debug-jtag port of riscv cores
michg/riscv32_lcc
michg/riscv32_beluga
c compiler beluga with riscv32 backend
michg/cproc_riscv32
michg/elftools_riscv32
assembler and linker for riscv32
michg/cparserlibfirm_riscv32
michg/pyhdlsim
michg/qbe_riscv32
michg/cdl_hardware
CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc
michg/cproc
C11 compiler (mirror)
michg/libfirm
graph based intermediate representation and backend for optimising compilers
michg/nmigen-yosim
Another simulation backend for nmigen using yosys
michg/cproc_riscv32_64
michg/ppci
A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python
michg/qbe_riscv32_64
michg/saxonsoc_trace
michg/spinalhdl
michg/vexriscv