michg

Pinned Repositories

cdl_hardware
CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc
Language:Python0 1 00
cparserlibfirm_riscv32
Language:C1 2 00
cproc
C11 compiler (mirror)
Language:C0 0 00
cproc_riscv32
Language:Verilog3 1 00
elftools_riscv32
assembler and linker for riscv32
Language:C2 2 10
pyhdlsim
Language:Python1 2 00
pyocdriscv32
Python script for controlling the debug-jtag port of riscv cores
Language:Verilog13 2 12
qbe_riscv32
Language:C1 1 00
riscv32_beluga
c compiler beluga with riscv32 backend
Language:C9 2 00
riscv32_lcc
Language:C11 5 16

michg's Repositories

michg/pyocdriscv32
Python script for controlling the debug-jtag port of riscv cores
Language:Verilog13 2 12
michg/riscv32_lcc
Language:C11 5 16
michg/riscv32_beluga
c compiler beluga with riscv32 backend
Language:C9 2 00
michg/cproc_riscv32
Language:Verilog3 1 00
michg/elftools_riscv32
assembler and linker for riscv32
Language:C2 2 10
michg/cparserlibfirm_riscv32
Language:C1 2 00
michg/pyhdlsim
Language:Python1 2 00
michg/qbe_riscv32
Language:C1 1 00
michg/cdl_hardware
CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc
Language:Python0 1 00
michg/cproc
C11 compiler (mirror)
Language:C0 0 00
michg/libfirm
graph based intermediate representation and backend for optimising compilers
Language:C0 2 00
michg/nmigen-yosim
Another simulation backend for nmigen using yosys
Language:Python0 1 00
michg/cproc_riscv32_64
Language:Verilog1 0
michg/ppci
A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python
Language:Python1 0
michg/qbe_riscv32_64
Language:C
michg/saxonsoc_trace
Language:Python2 01
michg/spinalhdl
Language:Scala1 0
michg/vexriscv
Language:Assembly