/register_interface

Generic Register Interface (contains various adatpers)

Primary LanguageSystemVerilogOtherNOASSERTION

Generic Register Interface

This repository contains a simple register interface definition as well as protocol adapters from APB, AXI-Lite, and AXI to said interface. Furthermore, it allows to generate a uniform register interface.

Read Timing

Read Timing

Write Timing

Write Timing

Register File Generator

We re-use lowrisc's register file generator to generate arbitrary configuration registers from an hjson description. See the the tool's description for further usage details.

We use the vendor tool util/vendor.py to get the sources and apply our custom patches on top.

./util/vendor.py vendor/lowrisc_opentitan.vendor.hjson --update

to re-vendor.