Pinned Repositories
adv_dbg_if
Advanced Debug Interface
hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
MNGTimetable
pulp_soc
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
bender
A dependency management tool for hardware projects.
FlooNoC
A Fast, Low-Overhead On-chip Network
iDMA
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
redundancy_cells
SystemVerilog IPs and Modules for architectural redundancy designs.
micprog's Repositories
micprog/hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
micprog/pulp_soc
micprog/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
micprog/axi_node
AXI X-Bar
micprog/bender
A dependency management tool for hardware projects.
micprog/cluster_interconnect
micprog/common_cells
Common SystemVerilog components
micprog/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
micprog/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
micprog/fpu_interco
micprog/gap_sdk
SDK for Greenwaves Technologies' GAP8 IoT Application Processor
micprog/hier-icache
micprog/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
micprog/icache-intc
micprog/icache_mp_128_pf
micprog/iDMA
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
micprog/mchan
micprog/opentitan
OpenTitan: Open source silicon root of trust
micprog/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
micprog/pulp-dsp
micprog/pulp-runtime
Simple runtime for Pulp platforms
micprog/pulp_cluster
The multi-core cluster of a PULP system.
micprog/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
micprog/ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
micprog/register_interface
Generic Register Interface (contains various adatpers)
micprog/regression_tests
micprog/riscv-rt
Minimal runtime / startup for RISC-V CPU's.
micprog/scm
micprog/SystemVerilog
SystemVerilog plugin for Sublime Text
micprog/tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)