Pinned Repositories
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
carfield
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
common_cells
Common SystemVerilog components
Deeploy
DNN Compiler for Heterogeneous SoCs
pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
pulp-dronet
A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP
pulpino
An open-source microcontroller system based on RISC-V
snitch_cluster
An energy-efficient RISC-V floating-point compute cluster.
pulp-platform's Repositories
pulp-platform/bender
A dependency management tool for hardware projects.
pulp-platform/mempool
A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
pulp-platform/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
pulp-platform/croc
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
pulp-platform/spatz
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
pulp-platform/pulp-sdk
pulp-platform/pulp_cluster
The multi-core cluster of a PULP system.
pulp-platform/redmule
pulp-platform/tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
pulp-platform/axi_riscv_atomics
AXI Adapter(s) for RISC-V Atomic Operations
pulp-platform/Deeploy
DNN Compiler for Heterogeneous SoCs
pulp-platform/pulp-runtime
Simple runtime for Pulp platforms
pulp-platform/pulp-trainlib
Floating-Point Optimized On-Device Learning Library for the PULP Platform.
pulp-platform/hyperbus
pulp-platform/clint
RISC-V Core Local Interrupt Controller (CLINT)
pulp-platform/obi
OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
pulp-platform/redundancy_cells
SystemVerilog IPs and Modules for architectural redundancy designs.
pulp-platform/llvm-project
pulp-platform/TeraNoC
An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
pulp-platform/apb_timer
APB Timer Unit
pulp-platform/MAGIA
Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
pulp-platform/picobello
whatever it means
pulp-platform/hwpe-ctrl
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
pulp-platform/magia-sdk
pulp-platform/control-pulp
pulp-platform/AraXL
pulp-platform/cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
pulp-platform/datamover
pulp-platform/ManyRVData
pulp-platform/axi_obi
SystemVerilog protocol converters between the PULP-platform AXI and OBI IPs