pulp-platform/carfield
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
TclNOASSERTION
Issues
- 0
Parameters cleanup
#271 opened by alex96295 - 0
- 0
Fix mailbox address map
#269 opened by alex96295 - 0
module 'xilinx_rom_bank_1024x22' not found
#267 opened by franktaTian - 2
Watchdog timer reset
#21 opened by alex96295 - 0
Use system DMA to perform bare-metal offload (BMO)
#264 opened by alex96295 - 3
Clip minimum number of external AXI masters to 1 due to PULP cluster limitations.
#249 opened by yvantor - 0
Documentation: describe OpenMP flow
#258 opened by alex96295 - 1
- 1
Move `slink_read_reg` to `cheshire_vip`
#215 opened by alex96295 - 0
Use dedicated `target/sim` folder for simulations
#236 opened by alex96295 - 14
make car-init fails
#238 opened by lmg260a - 2
Analyze AXI to AXILite conversion
#13 opened by alex96295 - 2
Unaligned read to Safety Island SPM fails
#93 opened by bluewww - 0
System-level printf from PULP cluster
#222 opened by yvantor - 0
Connect L2 margin configuration signals
#99 opened by alex96295 - 0
Align Bender IPs
#24 opened by alex96295 - 0
Speed up simulation
#100 opened by alex96295 - 0
- 4
- 1
- 0
Test secure boot
#126 opened by bluewww - 1
Some warm resets fail
#92 opened by bluewww - 1
Missing hyper ram sdf
#122 opened by bluewww - 5
Spurious latches
#55 opened by bluewww - 2
Track AXI4 crossbar scaling
#25 opened by alex96295 - 0
Add test for L2 ECC manager
#98 opened by alex96295 - 0
Fix isolate in carfield.sv
#85 opened by alex96295 - 0
Fix timer interrupt Xs in carfield
#86 opened by alex96295 - 0
Improve naming for Carfield's cores traces
#73 opened by alex96295 - 6
Align HARTIDs
#22 opened by alex96295 - 0
- 0
Propagate bootmode for safety Island
#64 opened by alex96295 - 1
- 4
- 3
SYNTHESIS ERROR
#26 opened by anga93 - 1