Clip minimum number of external AXI masters to 1 due to PULP cluster limitations.
yvantor opened this issue · 3 comments
There is an issue with this piece of logic. Since the PULP cluster has a separate CDC destination FIFO due to its different AXI ID widths respect to the rest of the SoC, if one wants to use a very basic Carfield configuration where Cfg.AxiExtNumMst becomes 0, that for has an iterative spanning from 0 to 0-1, and the code does not compile. To mitigate this, as a temporary solution we prevent Cfg.AxiExtNumMst from being zero with this workaround. The "final solution" would be to unify all the AXI IDs so that the PULP cluster does not need a dedicated port and the iterative of that for can freely span from 0 to Cfg.AxiExtNumMst, with a consequent increase in the area of the AXI crossbar that should be investigated.
This issue can be solved by moving the ID width converter inside PULP cluster, as done in spatz, and will prevent workarounds like the one mentioned in this issue from being used