Pinned Repositories
NN
opentitan
OpenTitan: Open source silicon root of trust
riscv
RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
carfield
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
hier-icache
pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
pulp-nn
pulp_cluster
The multi-core cluster of a PULP system.
soc_event_generator
anga93's Repositories
anga93/NN
anga93/opentitan
OpenTitan: Open source silicon root of trust
anga93/riscv
RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU