Pinned Repositories
acc-runtime
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
AGFIlib
AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
FeedforwardNet
Bottom up designed feed forward network functions for CNN applications
hls_dnn
Open-Dnn
Quantization-caffe
Quantization Methods for DNN Compression
T-DLA
TCOperator
microideax's Repositories
microideax/mytest
microideax/aws-software
microideax/split-engine
microideax/convAcc_imp
microideax/AGFIlib
microideax/fpga_caffe
microideax/UltraRam
Inferring URAM in VivadoHLS 2017.1
microideax/systolic-array
HLS implemented systolic array structure
microideax/spatial-filter-hdl
High Throughput Image Filters on FPGAs
microideax/convolution_strm
Example of an algorithm with optimal data access patterns
microideax/research-thermal-sensing
Dataset and source code used in the research "Human-Sensing: Low Resolution Thermal Array Sensor Data Classification of Location-Based Postures".
microideax/hls_dnn
microideax/caffe-twns
Implementation of Ternary Weight Networks In Caffe
microideax/CLAIMS
Claims is an in-memory parallel database prototype, which runs on clusters of shared-nothing servers and provides efficient and scalable data analysis.