mohamedtareq24
ECE student at Ain shams University Cairo, with hands on experience in ASICs & FPGA design flows.
Pinned Repositories
4_Channel_Logic_Analyzer
FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA
555-watch
digital watch based on 555 timer IC and 7447 decoder 74160 BCD counter and 7 segment dispalys
ASIC_implementation_of_PULPino_SoC
My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools
ASICs_Design_Diploma
RTL to GDSII flow of a low Power configurable multi clock digital system
ASU-ICL-Low-Cost-Brucella-Sensing-Solution
EIS based solution for sensing Brucella in milk based on ESP32 low cost MCU with MATLAB in the loop affiliated with Ain Shams University IC lab supervised by professor Hani Fikry
DSP_Custom_AXI_IPs
Work under progress.
IEEE_ASUSB_2023_Digital_Design_Workshop
IEEECUSB_Electronics_23_FinalProject
This is a documentation for the final project of IEEE CUSB 23 Digital Electonics Workshop, the project was FPGA implemented
My_Verification_work
A repo for my System Verilog testbenches with test benches for UART, I2C, SPI, FIFOs and Bus protocols like AMBA, AHB and WISHBONE
SPI_Memory_interface
The RTL for an SPI slave memory interface
mohamedtareq24's Repositories
mohamedtareq24/IEEECUSB_Electronics_23_FinalProject
This is a documentation for the final project of IEEE CUSB 23 Digital Electonics Workshop, the project was FPGA implemented
mohamedtareq24/My_Verification_work
A repo for my System Verilog testbenches with test benches for UART, I2C, SPI, FIFOs and Bus protocols like AMBA, AHB and WISHBONE
mohamedtareq24/4_Channel_Logic_Analyzer
FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA
mohamedtareq24/ASIC_implementation_of_PULPino_SoC
My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools
mohamedtareq24/ASICs_Design_Diploma
RTL to GDSII flow of a low Power configurable multi clock digital system
mohamedtareq24/DSP_Custom_AXI_IPs
Work under progress.
mohamedtareq24/SPI_Memory_interface
The RTL for an SPI slave memory interface
mohamedtareq24/IEEE_ASUSB_2023_Digital_Design_Workshop
mohamedtareq24/555-watch
digital watch based on 555 timer IC and 7447 decoder 74160 BCD counter and 7 segment dispalys
mohamedtareq24/ASU-ICL-Low-Cost-Brucella-Sensing-Solution
EIS based solution for sensing Brucella in milk based on ESP32 low cost MCU with MATLAB in the loop affiliated with Ain Shams University IC lab supervised by professor Hani Fikry
mohamedtareq24/ASU_SoC
mohamedtareq24/C-polynomails-long-divider
mohamedtareq24/ODE_solver_NIOS_II
NIOS II controlled hardware ODE solver implemented on Cyclone IV FPGA
mohamedtareq24/The-drone
A repository for a quadcopter project