design a 32-Bit single cycle MIPS microprocessor (RISC-Like Harvard Architecture), Using Verilog HDL. to test and verify the design we ran the following programs: -Get the factorial of 7. -Get the greatest common divisor (GCD) between 120 and 180. -Get the Fibonacci sequence.
32 BIT MIPS ARCHITESTURE
Vivado implementation
output of factorial of 7 Program.
output of GCD of 120 and 180 Proram.
the reference "Digital design and computer architecture" helped me a lot in designing the microprocessor