Pinned Repositories
AES-128
Advanced encryption standard implementation in Verilog.
ASIC-Design-of-Low-Power-Configurable-Multi-Clock-Digital-System-With-UART-Transceiver
RTL to GDS|| Implementation of a Digital System supporting Read, Write, Low-Power ALU Operation With/Without Operand Commands through core blocks operation with 50 MHz interfaced with 6.9 KHz UART peripheral.
ATM-SYSTEM
ATM-SYSTEM
Client-Queue-With-Verilog
Lorenz-by-Euler-integrator
mohos455
mohos455.github.io
Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes
Single-Cycle-MIPS-Processor
SPI-Master-Slave
UART-WITH-VERILOG
mohos455's Repositories
mohos455/AES-128
Advanced encryption standard implementation in Verilog.
mohos455/Single-Cycle-MIPS-Processor
mohos455/SPI-Master-Slave
mohos455/UART-WITH-VERILOG
mohos455/ASIC-Design-of-Low-Power-Configurable-Multi-Clock-Digital-System-With-UART-Transceiver
RTL to GDS|| Implementation of a Digital System supporting Read, Write, Low-Power ALU Operation With/Without Operand Commands through core blocks operation with 50 MHz interfaced with 6.9 KHz UART peripheral.
mohos455/ATM-SYSTEM
ATM-SYSTEM
mohos455/Client-Queue-With-Verilog
mohos455/Lorenz-by-Euler-integrator
mohos455/mohos455
mohos455/mohos455.github.io
Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes
mohos455/Single-Cycle-RISC-V-processor
mohos455/Spartan6-DSP48A1-With-Verilog
mohos455/Verilog