mohos455

mohos455's Stars

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog7.1k6724533

• sb2nov/resume

  Software developer resume in Latex

  Language:TeX5.3k41331.5k

• BrunoLevy/learn-fpga

  Learning FPGA, yosys, nextpnr, and RISC-V

  Language:C++2.6k8474246

• Obijuan/open-fpga-verilog-tutorial

  Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

  Language:Verilog7707016195

• splinedrive/kianRiscV

  RISC-V Linux SoC, marchID: 0x2b

  Language:C70428447

• riscv/learn

  Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

  557652165

• mikeroyal/RISC-V-Guide

  RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

  Language:Assembly52719543

• lowRISC/style-guides

  lowRISC Style Guides

  3696934123

• openhwgroup/core-v-cores

  CORE-V Family of RISC-V Cores

  20628115

• ikwzm/FPGA-SoC-Linux

  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de10-nano)

  Language:C159341257

• efabless/OpenLane

  This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

  Language:Python1416035

• google/sky90fd-pdk

  1079311

• ultraembedded/riscv_soc

  Basic RISC-V Test SoC

  Language:Verilog10310429

• The-OpenROAD-Project/asap7

  967306

• asinghani/open-eda-course

  Language:Jupyter Notebook52317

• fpgaemu/fpgaemu

  Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos School of Engineering & Computing Showcase.

  41303

• Centre-for-Hardware-Security/asap7_reference_design

  reference block design for the ASAP7nm library in Cadence Innovus

  Language:Verilog32309

• ahegazy/aes

  Advanced encryption standard implementation in verilog.

  Language:Verilog26539

• lucky-wfw/IC_System_Design

  Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, state machine, and so on. All designs have been validated by Testbench and FPGA functions.

  Language:Verilog241010

• karimmahmoud22/SystemVerilog-For-Verification

  Language:SystemVerilog22203

• nickson-jose/openlane_build_script

  This script builds openlane and all its dependencies on an Ubuntu (only) System.

  Language:Shell204624

• sure-trust/VLSI-Project-AXI-to-APB-Bridge

  Language:Verilog14202

• SeanZarzycki/openSPARC-FPU

  ASIC Design of the openSPARC Floating Point Unit

  Language:Verilog133

• lnis-uofu/TIGFET-10nm-SCLIB

  An open source standard cell library using TIGFET 10nm devices.

  Language:SourcePawn9703

• A-Hares/SPI-NTI-GP

  A Verilog RTL implementation of a Master/Slave Serial Peripheral Interface Block

  Language:Verilog5201

• EECS150/asic-project-sp24

  Language:C41502

• Gavin1999/APB_UART

  Design source of APB_UART, based on AMBA 3.0.

  Language:Verilog4100

• hossamfadeel/AI-Chip

  A list of ICs and IPs for AI, Machine Learning and Deep Learning.

  Language:PHP3000

• abdullah8a0/one-chan

  An FPGA-based Chess Engine and TPU

  Language:SystemVerilog2100

• mahmoudhalim/zero-riscy

  110