Introduction: In the dynamic landscape of computer architecture, the RISC-V instruction set has emerged as a beacon of innovation, offering an open and extensible foundation for processor design. As we navigate the intricate realm of RISC-V, this article serves as a compass, guiding us through the fundamental aspects of its instruction set and the intricacies of single-cycle and multi-cycle implementations. At the heart of RISC-V lies its instruction set architecture (ISA), characterized by a streamlined design philosophy that emphasizes simplicity, efficiency, and openness. As we delve into the RISC-V instruction set, we will decode the architecture's unique approach to command execution, exploring how it strikes a balance between performance and versatility. From its elegant simplicity to its comprehensive set of instructions, RISC-V beckons us to rethink the way processors interpret and execute commands. Venturing further, we will dissect the single-cycle implementation of RISC-V, where each instruction is executed in a single clock cycle. This efficient approach simplifies the pipeline and promises low-latency processing. We'll examine the intricacies of the single-cycle architecture, uncovering how it optimizes execution speed and resource utilization. Through detailed analysis, we aim to illustrate the strengths and limitations of the single-cycle paradigm, providing insights into its real-world applications and trade-offs.
Instruction Set Architecture: Within the expansive RISC-V Instruction Set Architecture (ISA), I have taken a deliberate approach by carefully choosing a range of instructions that span various formats, including computational, control flow, and memory access. This selective approach will guide us as we design a custom Datapath and precisely specify the control signals needed to execute our chosen instructions efficiently. The instruction set in RISC-V is organized into distinct instruction formats, with each format comprising individual "fields." These fields are essentially separate unsigned integers, each serving as a dedicated container for conveying precise information about the intended operation to be executed.
Supported Instructions:
Basic Architecture : I have modified the architecture to add more Instruction Set.
Basic Control unit :
Simulatiom :
The code
The result :
another Code :
Results :
Elaboration Design using VIVADO:
Synthesis using VIVADO:
Reference :
1- Digital Design and Computer Architecture Sarah Harris ,David Harris.
2-The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2