msawan12's Stars
Sai-Manish/Tomasulo-based-RV32I-processor
StephenGrider/EthereumCasts
Companion repo to an Ethereum/Solidity course on Udemy
arjunrajasekharan/Tomasulo-Architecture
Simulation of the Tomasulo algorithm using python and verilog.Python code has been included to simulate dynamic instruction scheduling.This project was done as the part of Computer Architecture course.
cla7aye15I4nd/trivial-riscv-cpu
A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
navneet-kour/Tomasulo_Verilog
Implemented a 4 staged pipelined out of order RISC-V processor which uses tomasulo algorithm with reservation stations and reorder buffers. This was a course assignment in Processor Architecture course.
eisl-nctu/falco
A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.
OscarLGH/Oscar-RVO3-Processor
Oscar RISC-V Out Of Order Processor
Patt-Senior-Design/core-design
Out-of-Order RISC-V Core Design in Behavioral Verilog and RTL
GeekAlexis/superscalar-mips
A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
bluespec/Toooba
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
YanB25/Tomasulo
An out-of-order execution algorithm for pipeline CPU, implemented by verilog
ridecore/ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.