/trivial-riscv-cpu

A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.

Primary LanguageVerilogGNU General Public License v2.0GPL-2.0

trivial-riscv

This project is a trivial riscv cpu with tomasulo implemented in Verilog HDL, which is a course project of Computer Architecture, ACM Class @ SJTU.

越是强大的设计，有时可能会令人越痛苦

Design

  • name: Error Isla
  • ISA: RISCV 32I
  • tomasulo algorithm (out-of-order execution)
  • 3-stages pipeline (fetch, dispatch, execute)
  • 2-set associative 512B Instruction Cache (Replacing Policy: FIFO)
  • IF Prefetch: Non-stop fetching instruction
  • multiple ALU(Arithmetic Logic Unit)
  • Segment LED timer, LED light game
  • Direct map Data Cache
  • Store Buffer

Performance

  • stably running on FPGA (200MHz, 81920 hours)
  • IPC = analysing

Todo

  • Load buffer
  • Instruction dual issue
  • Branch Prediction(BTB)
  • Interactive IO

Reference