cla7aye15I4nd/trivial-riscv-cpu
A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
VerilogGPL-2.0
Issues
- 1
Issue while running project
#2 opened - 1
common_defs.v
#1 opened