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Vedant-02/Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
abhinavprakash199/2D-Coordinate-Rotation-and-Vectoring-based-Design-Methodology-CORDIC-using-Verilog-HDL
is22mtech14003/2D-Coordinate-Rotating-and-Vectoring-based-Design-Methodology-CORDIC-using-Verilog-HDL