muhammad-sayed-mahdy/pipelined-processor

5-stage pipelined microprocessor with data forwarding, hazard detection and dynamic branch prediction written in VHDL

VHDL

Issues

Out branch prediction results in Fetch/Decode intermediate register
#4 opened 5 years ago by KhaledMoataz
0
use incremented PC instead
#2 opened 5 years ago by KhaledMoataz
0
Take intro consideration 2 words instructions in fetch
#3 opened 5 years ago by KhaledMoataz
0
use curr_address instead
#1 opened 5 years ago by KhaledMoataz
0