nalevihtkas

1st-CLaaS

Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

2-D-FIR-Filter-Design

5-DAYS-VSD-LOW-POWER-USING-NGSPICE

5 DAYS LOW POWER DESING WORKSHOP USING NGSPICE

adder

reversible floating point adder

Adder-models-for-approximate-computing

This repository includes python modules to handle integer and floating point data and process them with exact and approximate adders. The crude input in decimal form is converted into standard binary representations and then processed. The errors incorporated can directly be monitored for analyzing the performance of the approximate design.

adder_networks

Store of prefix tree adder HDL, diagrams, and implementation results

AdderCircuitGenerator

This script generates and analyzes prefix tree adders.

Advanced-System-on-Chip-Design-Education-Kit

Advanced System on Chip Design Education Kit

EDA-tools-in-ASIC-Design-flow

EDA tools largely use heuristic methods to arrive at solutions for the various stages of design flow. The implementation of general algorithms and data structures becomes more interesting when mixed with the constraint requirements of the VLSI Design. This repository includes the core implementation of a few of these algorithms and methods, pertaining to the Place and Route steps.

vlsi-design-automation

Python implementation of VLSI Design Automation as a part of EC440 VLSI CAD project.

nalevihtkas/Approximate-8x8-multiplier-designs

Implementation of approximate 8x8 multipliers using 4x4 multipliers with 4:2 compressor.

nalevihtkas/Approximate_Multiplier

nalevihtkas/DCT-using-approximate-multiplier

Implemented an 8 point 1-D DCT using approximate carry reverse adder based multiplier

nalevihtkas/deductive-fault-sim

Python code for deductive fault simulation in digital VLSI testing

nalevihtkas/Digital-ASIC-LAB

Verilog Codes for various Design

nalevihtkas/examples

nalevihtkas/HDLBits-solutions

This repository contains solutions to the problems statements from HDLbits website (https://hdlbits.01xz.net/wiki/Main_Page)

nalevihtkas/imagemergingusingapproximatemultipliers

Image Merging with Verilog-Designed Approximate Multipliers using Alpha Blending

nalevihtkas/intel-training-modules

nalevihtkas/JPEG-DCT

DCT implement with Verilog and Python

nalevihtkas/Libero-SoC-Design-Suite-Tcl-Examples

Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.

nalevihtkas/msvsd4bituc

VSD Mixed-signal PD Research Program

nalevihtkas/optiVLSI

A library for fast and optimized VLSI Computer-Aided-Design algorithms

nalevihtkas/Physical-Design

This Repository discusses the Physical Design of Integrated Citrcuits along with the steps and other necessary files.

nalevihtkas/pso_combinational_circuits

This project describes the use of the Particle Swarm Optimization algorithm to reduce the gate count in combinational logic circuits

nalevihtkas/rggen

Code generation tool for configuration and status registers

nalevihtkas/RISCV-HDP

Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)

nalevihtkas/sta_basics_course

Introductory course into static timing analysis (STA).

nalevihtkas/Static-Timing-Analysis-Full-Course

Static Timing Analysis Full Course

nalevihtkas/systemverilog

SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow

nalevihtkas/TCL-programming

nalevihtkas/TCL-Scripting

Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference

nalevihtkas/Verification-of-a-cominational-adder-using-UVM

nalevihtkas/Verification-of-Adder-with-uvm

Verification-of-Adder-with-uvm

nalevihtkas/Visruat-VSD-HDP

all material for the VSD-HDP program

nalevihtkas/vlsi-circuit-partitioning-algorithms

Course Project - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

nalevihtkas/VLSI-Laboratory-NIT-Rourkela

Laboraory manuals and Discussion

nalevihtkas/VSD-IAT-Sign-off-Timing-Analysis---Basics-to-Advanced

5 DAY WORKSHOP

nalevihtkas/VSD-IAT-Sign-off-Timing-Analysis-Basics-to-Advanced

In this workshop we studied the concepts involved in STA from basics to advanced, with the help of open source STA tools and libraries.

nalevihtkas/VSD-TCL

pre requistes of frontend