Pinned Repositories
1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
2-D-FIR-Filter-Design
5-DAYS-VSD-LOW-POWER-USING-NGSPICE
5 DAYS LOW POWER DESING WORKSHOP USING NGSPICE
adder
reversible floating point adder
Adder-models-for-approximate-computing
This repository includes python modules to handle integer and floating point data and process them with exact and approximate adders. The crude input in decimal form is converted into standard binary representations and then processed. The errors incorporated can directly be monitored for analyzing the performance of the approximate design.
adder_networks
Store of prefix tree adder HDL, diagrams, and implementation results
AdderCircuitGenerator
This script generates and analyzes prefix tree adders.
Advanced-System-on-Chip-Design-Education-Kit
Advanced System on Chip Design Education Kit
EDA-tools-in-ASIC-Design-flow
EDA tools largely use heuristic methods to arrive at solutions for the various stages of design flow. The implementation of general algorithms and data structures becomes more interesting when mixed with the constraint requirements of the VLSI Design. This repository includes the core implementation of a few of these algorithms and methods, pertaining to the Place and Route steps.
vlsi-design-automation
Python implementation of VLSI Design Automation as a part of EC440 VLSI CAD project.
nalevihtkas's Repositories
nalevihtkas/Linux-Commands-for-VLSI-Engineers
Below are basic Linux command which may be useful for VLSI Engineers while working in Linux
nalevihtkas/RISC-V_Core_4_Stage
RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set
nalevihtkas/Parallel-FIR-Filter
VHDL implementation of a parallel FIR filter
nalevihtkas/Multi-cycle-CPU
code with vivado HDL
nalevihtkas/project_Automated_Circuit_To_VLSI_Layout
Project Name: Automated Circuit To MAGIC VLSI layout Using Open Source EDA Tools
nalevihtkas/VLSI
contains all the practice codes for perl, TCL and python
nalevihtkas/Image-Classification-using-CNN-on-FPGA
Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
nalevihtkas/VLSI_Physical_Design_Tool
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
nalevihtkas/vsdsram_sky130-1
Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns
nalevihtkas/vsdmixedsignalflow
This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.
nalevihtkas/CAD_for_IC_Design
This repository contains all the codes (implemented in python) used in different stages of VLSI back-end flow.
nalevihtkas/vsdDevBoard_v0
nalevihtkas/vsdstdcelldesign
This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.
nalevihtkas/Standard-Cell-design-and-characterization-of-Inverter-in-OpenLane
nalevihtkas/Problem_Solving
Solved problems(Questions and Solution)
nalevihtkas/Hardware-Description-Languages-for-FPGA-Design
My HDL activities appear here. This is for my personal use. PPT's copyrights to University of Colorado Boulder.
nalevihtkas/FPGA-FIR-Filter
Lecture about FIR filter on an FPGA
nalevihtkas/Hardware_implementation_of_RGB_to_gray
【Verilog&vivado】彩色图像转灰度的硬件实现
nalevihtkas/vsdOSPowerCalc
nalevihtkas/FIR-Filter-Design-by-Convex-Optimization-Using-Directed-Iterative-Rank-Refinement-Algorithm
nalevihtkas/EDA-tools-in-ASIC-Design-flow
EDA tools largely use heuristic methods to arrive at solutions for the various stages of design flow. The implementation of general algorithms and data structures becomes more interesting when mixed with the constraint requirements of the VLSI Design. This repository includes the core implementation of a few of these algorithms and methods, pertaining to the Place and Route steps.
nalevihtkas/Optimization-of-8-bit-Vedic-Multiplier-using-reversible-logic
nalevihtkas/Low-Power-Unsigned-Multiplier
Implementation of an approximate low power unsigned multiplier with configurable error recovery
nalevihtkas/VSD-Static-Timing-analysis-II
nalevihtkas/test_wafer_generator
Used to characterization of standard cells and Test structures
nalevihtkas/Parallel_FIR_Filter_V1
Transposed FIR filter implementation
nalevihtkas/Book-Python-Programming-Problem-Solving-Packages-and-Libraries
Python book
nalevihtkas/Astrosoft
Astrosoft is a free Indian Astrology software program for Astrologers.
nalevihtkas/SystemVerliog-9-tap-digital-filter
Designing a 9-tap digital filter in SystemVerilog, testing it in a behavioural simulation and verifying its output against a software model. Then using Quartus to perform a static timing analysis to ensure that the design meets performance requirements.
nalevihtkas/open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools