Pinned Repositories
ahblite2apb
AHBLite bus to APB4 bridge
AMBA_APB_SRAM
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
apb-uart-uvm-env
apb_spi_master
apb_sram
axi4lite_100mbps_mac
axi_dma
General Purpose AXI Direct Memory Access
BrianHG-DDR3-Controller
DDR3 Controller v1.50, 16 read/write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included. HDMI video controller included.
Interleaved-Synthesizable-Synchronization-FIFOs
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs
NandFlashController
AXI Interface Nand Flash Controller (Sync mode)
nguyentrungduong's Repositories
nguyentrungduong/airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
nguyentrungduong/apb_uvc_verilator
APB UVC ported to Verilator
nguyentrungduong/cocotbext-ahb
Cocotb AHB Extension - AHB VIP
nguyentrungduong/DDR3_Controller
nguyentrungduong/ddr5_phy
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
nguyentrungduong/Design-and-ASIC-Implementation-of-UART
This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II
nguyentrungduong/EE628
EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)
nguyentrungduong/Embedded-Engineering-Roadmap
A comprehensive roadmap for aspiring Embedded Systems Engineers, featuring a curated list of learning resources.
nguyentrungduong/embeddedsw.github.io
Repo is used to store Doxygen documentation for BM drivers
nguyentrungduong/fixture
Library of templates for analog blocks and strategies to model them in a digital environment
nguyentrungduong/FlooNoC
A Fast, Low-Overhead On-chip Network
nguyentrungduong/FPGA-USB-Device
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
nguyentrungduong/gcm
nguyentrungduong/hbird-sdk
OpenSource HummingBird RISC-V Software Development Kit
nguyentrungduong/hdl
HDL libraries and projects
nguyentrungduong/i2c_slave
nguyentrungduong/JLSD
nguyentrungduong/len5
LEN5 is a coonfigurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
nguyentrungduong/msdsl
Automatic generation of real number models from analog circuits
nguyentrungduong/phoeniX
phoeniX RISC-V Processor
nguyentrungduong/pyuvm_primer
Examples for using pyuvm
nguyentrungduong/redis
Redis is an in-memory database that persists on disk. The data model is key-value, but many different kind of values are supported: Strings, Lists, Sets, Sorted Sets, Hashes, Streams, HyperLogLogs, Bitmaps.
nguyentrungduong/RISC-V
Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
nguyentrungduong/RISC-V-Assembly-Language-Programming
Source Code
nguyentrungduong/sample_and_hold
Fully differential sample and hold circuit
nguyentrungduong/SoomRV
A simple superscalar out of order RISC-V (micro)processor
nguyentrungduong/super-riscv
Superscalar dual-issue RISC-V processor
nguyentrungduong/ttpoe
nguyentrungduong/Viterbi-Decoder-in-Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
nguyentrungduong/xkDLA
xkDLA：XinKai Deep Learning Accelerator (RTL)