Pinned Repositories
ahblite2apb
AHBLite bus to APB4 bridge
AMBA_APB_SRAM
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
apb-uart-uvm-env
apb_spi_master
apb_sram
axi4lite_100mbps_mac
axi_dma
General Purpose AXI Direct Memory Access
BrianHG-DDR3-Controller
DDR3 Controller v1.50, 16 read/write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included. HDMI video controller included.
Interleaved-Synthesizable-Synchronization-FIFOs
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs
NandFlashController
AXI Interface Nand Flash Controller (Sync mode)
nguyentrungduong's Repositories
nguyentrungduong/BrianHG-DDR3-Controller
DDR3 Controller v1.50, 16 read/write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included. HDMI video controller included.
nguyentrungduong/apb-uart-uvm-env
nguyentrungduong/activecore
Hardware generation library based on "Kernel IP" (KIP) cores (microarchitectural programmable templates)
nguyentrungduong/ArmleoCPU
Multicore RISC-V CPU RV32IMA w/ MMU, Cache capable of booting Linux. Work in progress to execute first instruction
nguyentrungduong/awesome-dv
Awesome ASIC design verification
nguyentrungduong/awesome-semiconductor-startups
List of awesome semiconductor startups
nguyentrungduong/axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
nguyentrungduong/berkeley-hardfloat
nguyentrungduong/Caravel_FPU
nguyentrungduong/caravel_user_project_analog_example
DDR3 SSTL Test analog caravel user project
nguyentrungduong/CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).
nguyentrungduong/corundum
Open source, high performance, FPGA-based NIC
nguyentrungduong/DFFRAM
Standard Cell Library based Memory Compiler using DFF cells
nguyentrungduong/e203_hbirdv2
The Ultra-Low Power RISC-V Core
nguyentrungduong/GPCore
This is the base repo for our graduation project in AlexU 21
nguyentrungduong/Hazard3
3-stage RV32IMACZb* processor with debug
nguyentrungduong/iob-cache
Verilog configurable cache
nguyentrungduong/litedram
Small footprint and configurable DRAM core
nguyentrungduong/ML-YouTube-Courses
📺 A repository to index and organize the latest machine learning courses found on YouTube.
nguyentrungduong/mmRISC-1
RISC-V RV32IMAFC Core for MCU
nguyentrungduong/NaxRiscv
nguyentrungduong/NutShell
RISC-V SoC designed by students in UCAS
nguyentrungduong/openc910
OpenXuantie - OpenC910 Core
nguyentrungduong/Pathsy
Simple Path Tracer on an FPGA
nguyentrungduong/pspin
PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
nguyentrungduong/riscv-dv
Random instruction generator for RISC-V processor verification
nguyentrungduong/rv-pc
nguyentrungduong/siliconcompiler
SiliconCompiler is an open source build system that automates translation from source code to silicon.
nguyentrungduong/vroom
VRoom! RISC-V CPU
nguyentrungduong/wav-lpddr-hw
Wavious DDR (WDDR) Physical interface (PHY) Hardware