niuguobiao

niuguobiao's Stars

• KindaM3h/SpaceVNXDaughterBoard

  JESD204B ADC and DAC SYZYGY Pod.

  41

• elhep/FMC_ADC_4CHA_1G_12B

  FMC ADC 4x1GS/s 12B JESD204B

  57

• Anthon1e/JESD204B-Transport-and-Data-Link-Layer

  Implementation of JESD204B Transport Layer & part of Data Link Layer

  Language:Verilog2515

• afiskon/fpga-ssd1306-to-vga

  ICE40 FPGA configuration: SSD1306 to VGA converter

  Language:SystemVerilog72

• lupyuen/fpga_oled_ssd1306

  FPGA controller for SSD1306 OLED module on SPI. Optimised for GOWIN FPGA

  Language:Forth123

• ExperimentalPhysics/StepMotorDriver

  FPGA driver of step motor on CIC-560 training system designing for plazmatrone sample 1-d positioning

  Language:SystemVerilog21

• sanguinius121/CIC-filter-FPGA

  Language:Verilog1

• Istzqy/CIC-Filter

  关于CIC滤波器、ISOP补偿器、HB滤波器的相关Matlab仿真与FPGA工程

  Language:Verilog51

• hukenovs/dsp-theory

  Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

  Language:Jupyter Notebook981178

• Dudestin/udp_camera_streaming

  Video streaming at FPGA using OV2640

  Language:Verilog21

• BigPig-Bro/udp_gmii_ov5640

  本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。

  Language:V40

• DIWEIKA/QtDemo_UDP_v2.2.4

  上位机软件与下位机FPGA采集卡实现UDP通信，接收发送的正弦波信号帧，并保存到本地文件

  Language:C++105

• Essenceia/low-latency-ethernet

  RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

  Language:Verilog2014

• KoroB14/DVP_to_UDP

  Uncompressed video uver UDP using 1000BASE-T Ethernet on Cyclone IV FPGA

  Language:Verilog279

• adamchristiansen/fpga-ethernet-udp

  An HDL design for sending data over Ethernet

  Language:SystemVerilog3212

• Shaf3y99/OFDM_Verilog

  This repo is about implementing OFDM transmitter on FPGA (Zedboard) using Verilog language and Vivado simulator

  Language:Verilog72

• darshangm92/Implementation-of-CDMA-Transmitter-and-Receiver-using-Intel-DE2i-150-FPGA-board

  Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the digital modulation technique and Altera FFT MegaCore Function has been used to implement the Inverse Fast Fourier Transform block. The output of the OFDM transmitter is displayed on the monitor by implementing VGA Controller.

  Language:Verilog174

• darshangm92/Implementation-of-OFDM-Transmitter-using-Intel-DE2i--150-FPGA-board

  Using the Quartus II software, a OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the digital modulation technique and Altera FFT MegaCore Function has been used to implement the Inverse Fast Fourier Transform block. The output of the OFDM transmitter is displayed on the monitor by implementing VGA Controller

  Language:Coq139

• ziruizhu/ofdm

  Toy OFDM Communication System with FPGA

  Language:Verilog104

• FlyHighInSky/OFDM-on-FPGA

  128

• brianhill11/FPGA-CNN

  This repo is for ECE44x (Fall2015-Spring2016)

  Language:SystemVerilog1914

• WangXuan95/UniPlug-FPGA

  一个FPGA核心板设计，体积小、低成本、易用、扩展性强。

  Language:Verilog7414

• projf/display_controller

  FPGA display controller with support for VGA, DVI, and HDMI.

  Language:Verilog21432

• jvitkauskas/Altera-Cyclone-IV-board-V3.0

  Documentation for Chinese ALTERA Cyclone IV EP4CE6 FPGA Development Board

  Language:PureBasic11446

• UofT-HPRC/fpga-bpf

  A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark

  Language:Verilog4412

• damdoy/fpga_image_processing

  IP operations in verilog (simulation and implementation on ice40)

  Language:Verilog5214

• GeneralZDS/FPGA-DCNN-Accelerator

  基于HLS的高效深度卷积神经网络FPGA实现方法

  Language:Ada6615

• John-Leitch/fpga-md5-cracker

  A 64-stage pipelined MD5 implementation written in verliog. Runs reliably on a DE0-Nano at 100mhz, computing 100 million hashes per second.

  Language:Verilog6717

• lulinchen/cnn_open

  A hardware implementation of CNN, written by Verilog and synthesized on FPGA

  Language:Coq21173

• padhi499/Image-Classification-using-CNN-on-FPGA

  Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

  Language:Verilog11525